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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68HC705C9A
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M68HC05
Microcontrollers
MC68HC705C9A/D Rev. 4, 2/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC68HC705C9A
Freescale Semiconductor, Inc...
Advance Information
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc.
(c) Motorola, Inc., 2002
MC68HC705C9A -- Rev. 4.0 MOTOROLA
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Revision History
Revision History
Date Revision Level Description Format update to current publication standards October, 2001 3.0 Figure 12-10. SPI Slave Timing Diagram -- Corrected labels for MISO and MOSI and subtitle for part b. Figure 8-3. Timer Status Register (TSR) -- Corrected address designator from $0012 to $0013. Page Number(s) N/A 145 78
February, 2002
4.0
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MC68HC705C9A -- Rev. 4.0 MOTOROLA
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List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 47 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . 67 Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . 69 Section 8. Capture/Compare Timer . . . . . . . . . . . . . . . . . 73 Section 9. Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . 85 Section 10. Serial Peripheral Interface (SPI). . . . . . . . . 103 Section 11. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 115 Section 12. Electrical Specifications. . . . . . . . . . . . . . . 131 Section 13. Mechanical Specifications . . . . . . . . . . . . . 147 Section 14. Ordering Information . . . . . . . . . . . . . . . . . 151 Appendix A. EPROM Programming. . . . . . . . . . . . . . . . 153 Appendix B. M68HC05Cx Family Feature Comparisons . . . . . . . . . . . . . . . . 157
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List of Sections
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MC68HC705C9A -- Rev. 4.0 MOTOROLA
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Advance Information -- MC68HC705C9A
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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1.2 1.3 1.4
1.5 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.1 Port B Mask Option Register (PBMOR) . . . . . . . . . . . . . . . . 26 1.5.2 C12 Mask Option Register (C12MOR). . . . . . . . . . . . . . . . . 27 1.6 Software-Programmable Options (MC68HC05C9A Mode Only) . . . . . . . . . . . . . . . . . . . . . . . 29
1.7 Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.2 VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.3 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.4 OSC1 andOSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.7.5 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.6 TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.7 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.8 PA0-PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.7.9 PB0-PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.7.10 PC0-PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.7.11 PD0-PD5 and PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Table of Contents Section 2. Memory
2.1 2.2 2.3 2.4 2.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 EPROM Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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2.6 2.7
Section 3. Central Processor Unit (CPU)
3.1 3.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.2 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.3 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.3.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.5 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 49
Section 4. Interrupts
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Non-Maskable Software Interrupt (SWI). . . . . . . . . . . . . . . . . . 53 External Interrupt (IRQ or Port B) . . . . . . . . . . . . . . . . . . . . . . . 53 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Table of Contents
Section 5. Resets
5.1 5.2 5.3 5.4 5.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .60
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5.6 MC68HC05C9A Compatible COP . . . . . . . . . . . . . . . . . . . . . . 60 5.6.1 C9A COP Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.6.2 C9A COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.7 5.8 5.9 MC68HC05C12A Compatible COP . . . . . . . . . . . . . . . . . . . . . 63 MC68HC05C12A Compatible COP Clear Register . . . . . . . . . 64 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.10 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.10.1 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.10.2 STOP Instruction Disable Option . . . . . . . . . . . . . . . . . . . . . 65
Section 6. Low-Power Modes
6.1 6.2 6.3 6.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Section 7. Input/Output (I/O) Ports
7.1 7.2 7.3 7.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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Table of Contents
7.5 7.6 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Section 8. Capture/Compare Timer
8.1 8.2 Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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8.3 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.3.1 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.3.2 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 8.4 Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 8.4.1 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 8.4.2 Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.4.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.4.4 Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.4.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.4.6 Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.5 8.6 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Section 9. Serial Communications Interface (SCI)
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SCI Receiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SCI Transmitter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Receiver Wakeup Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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9.10 9.11 9.12 9.13
Address Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Receive Data In (RDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Start Bit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Transmit Data Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
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9.14 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.14.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.14.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 9.14.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 9.14.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.14.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Section 10. Serial Peripheral Interface (SPI)
10.1 10.2 10.3 Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.4.1 Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . 105 10.4.2 Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . 105 10.4.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.4.4 Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 10.6.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . 109 10.6.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . 111 10.6.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . .113
Section 11. Instruction Set
11.1 11.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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Table of Contents
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .119 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 120 11.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .123 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 11.5 11.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Section 12. Electrical Specifications
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.0-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 135 3.3-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 136 5.0-Vdc Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.3-Vdc Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10 5.0-Vdc Serial Peripheral Interface Timing . . . . . . . . . . . . . . . 142 12.11 3.3- Vdc Serial Peirpheral Interface Timing . . . . . . . . . . . . . . 143
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Section 13. Mechanical Specifications
13.1 13.2 13.3 13.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . . 150
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13.5 13.6
Section 14. Ordering Information
14.1 14.2 14.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Appendix A. EPROM Programming
A.1 A.2 A.3 A.4 A.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Programming Register (PROG) . . . . . . . . . . . . . . . . . . . . . . .154
Appendix B. M68HC05Cx Family Feature Comparisons
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List of Figures
Figure 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 2-1 2-2 2-3 2-4 3-1 3-2 4-1 5-1 5-2 5-3 5-4 5-5 5-6 6-1
Title
Page
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Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Port B Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Option Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 C9A Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 40-Pin PDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 30 42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 31 44-Lead PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 32 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 33 C9A Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 C12A Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power-On Reset and RESET . . . . . . . . . . . . . . . . . . . . . . . . . . 59 C9A COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 COP Reset Register (COPRST). . . . . . . . . . . . . . . . . . . . . . . .61 COP Control Register (COPCR). . . . . . . . . . . . . . . . . . . . . . . .62 COP Clear Register (COPCLR) . . . . . . . . . . . . . . . . . . . . . . . .64 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .68
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List of Figures
Figure 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 Title Page
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Capture/Compare Timer Block Diagram. . . . . . . . . . . . . . . . . . 74 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . . 76 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Timer Registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . .79 Alternate Timer Registers (ATRH and ATRL). . . . . . . . . . . . . . 80 Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . . . 81 Output Compare Registers (OCRH and OCRL) . . . . . . . . . . . . 82
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9-1 Serial Communications Interface Block Diagram . . . . . . . . . . . 87 9-2 Rate Generator Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9-3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9-4 SCI Examples of Start Bit Sampling Techniques . . . . . . . . . . . 92 9-5 SCI Sampling Technique Used on All Bits . . . . . . . . . . . . . . . . 92 9-6 SCI Artificial Start Following a Frame Error . . . . . . . . . . . . . . . 93 9-7 SCI Start Bit Following a Break . . . . . . . . . . . . . . . . . . . . . . . .94 9-8 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9-9 SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . . 95 9-10 SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . . 96 9-11 SCI Status Register (SCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9-12 Baud Rate Register (BAUD) . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10-1 10-2 10-3 10-4 10-5 10-6 12-1 12-2 12-3 Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . . 107 Serial Peripheral Interface Master-Slave Interconnection . . . 108 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 PI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Maximum Supply Current vs Internal Clock Frequency, VDD = 5.5 V. . . . . . . . . . . . . . . . . . . . . . 137 Maximum Supply Current vs Internal Clock Frequency, VDD = 3.6 V. . . . . . . . . . . . . . . . . . . . . . 137
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List of Figures
Figure 12-4 12-5 12-6 12-7 12-8 12-9 12-10
Title
Page
TCAP Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . 139 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 140 Power-On Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . . 141 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 40-Pin Plastic DIP Package (Case 711-03) . . . . . . . . . . . . . . 148 42-Pin Plastic SDIP Package (Case 858-01) . . . . . . . . . . . . . 148 44-Lead PLCC (Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . 149 44-Lead QFP (Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . 150 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . .154
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13-1 13-2 13-3 13-4 A-1
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List of Tables
Table 4-1
Title
Page
Vector Addresses for Interrupts and Resets. . . . . . . . . . . . . . .52 COP Timeout Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . . . 101 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 119 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .120 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 122 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 123 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 M68HC05Cx Feature Comparison . . . . . . . . . . . . . . . . . . . . . 158
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5-1 9-1 9-2 10-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 14-1 A-1 A-2 B-1
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Section 1. General Description
1.1 Contents
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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1.3 1.4
1.5 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.1 Port B Mask Option Register (PBMOR) . . . . . . . . . . . . . . . . 26 1.5.2 C12 Mask Option Register (C12MOR). . . . . . . . . . . . . . . . . 27 1.6 Software-Programmable Options (MC68HC05C9A Mode Only) . . . . . . . . . . . . . . . . . . . . . . . 29
1.7 Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.2 VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.3 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.4 OSC1 andOSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.7.5 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.6 TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.7 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.7.8 PA0-PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.7.9 PB0-PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.7.10 PC0-PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.7.11 PD0-PD5 and PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.2 Introduction
The MC68HC705C9A HCMOS microcomputer is a member of the M68HC05 Family. The MC68HC705C9A is the EPROM version of the MC68HC05C9A and also can be configured as the EPROM version of
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General Description
the MC68HC05C12A. The MC68HC705C9A memory map consists of 12,092 bytes of user EPROM and 176 bytes of RAM when it is configured as an MC68HC05C12A and 15,932 bytes of user EPROM and 352 bytes of RAM when configured as an MC68HC05C9A. The MC68HC705C9A includes a serial communications interface, a serial peripheral interface, and a 16-bit capture/compare timer.
1.3 Features
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Features include: * * * * * * * * * * * * * * * Programmable mask option register (MOR) for C9A/C12A configuration Programmable MOR for port B pullups and interrupts Popular M68HC05 central processor unit (CPU) 15,932 bytes of EPROM (12,092 bytes for C12A configuration) 352 bytes of RAM (176 for C12A configuration) Memory mapped input/output (I/O) 31 bidirectional I/O lines (24 I/O + 6 input only for C12A configuration) with high current sink and source on PC7 Asynchronous serial communications interface (SCI) Synchronous serial peripheral interface (SPI) 16-bit capture/compare timer Computer operating properly (COP) watchdog timer and clock monitor Power-saving wait and stop modes On-chip crystal oscillator connections Single 3.0 volts to 5.5 volts power supply requirement EPROM contents security(1) feature
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the EPROM difficult for unauthorized users.
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General Description Features
BOOT ROM -- 239 BYTES
USER EPROM -- 15,936 BYTES PA7 USER RAM --352 BYTES DATA DIRECTION REGISTER A PA6 PA5 PORT A PA4 PA3 PA2 PA1 PA0
CPU CONTROL
ARITHMETIC/LOGIC UNIT ACCUMULATOR
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IRQ M68HC05 MCU
INDEX REGISTER RESET RESET PULLUP ENABLE REGISTER B
DATA DIRECTION REGISTER B
STACK POINTER 00000011 PROGRAM COUNTER
PB7 PB6 PB5 PORT B PB4 PB3 PB2 PB1 PB0
CONDITION CODE REGISTER 111HI CPU CLOCK OSC1 OSC2 INTERNAL OSCILLATOR DIVIDE BY TWO NCZ
DATA DIRECTION REGISTER C
PC7 PC6 PC5 PORT C PC4 PC3 PC2 PC1 PC0
COP WATCHDOG
INTERNAL CLOCK
DIVIDE BY FOUR TIMER CLOCK CAPTURE/ COMPARE TIMER BAUD RATE GENERATOR SPI SS SCK MOSI MISO VDD VSS SCI POWER TDO RDI
PD7 DATA DIRECTION REGISTER D
TCAP TCMP
PD5/SS PORT D PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI
Figure 1-1. Block Diagram
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General Description 1.4 Configuration Options
The options and functions of the MC68HC705C9A can be configured to emulate either the MC68HC05C9A or the MC68HC05C12A. The ROM device MC68HC05C9A has eight ROM mask options to select external interrupt/internal pullup capability on each of the eight port B bits. Other optional features are controlled by software addressable registers during operation of the microcontroller. These features are IRQ sensitivity and memory map configuration.
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On the ROM device MC68HC05C12A, all optional features are controlled by ROM mask options. These features are the eight port B interrupt/pullup options, IRQ sensitivity, STOP instruction disable, and COP enable. On the MC68HC705C9A the ROM mask options of the MC68HC05C9A and the MC68HC05C12A are controlled by mask option registers (MORs). The MORs are EPROM registers which must be programmed appropriately prior to operation of the microcontroller. The software options of the MC68HC05C9A are implemented by identical software registers in the MC68HC705C9A. When configured as an MC68HC05C9A: * The entire 16K memory map of the C9A is enabled, including dualmapped RAM and EPROM at locations $0020-$004F and $0100-$017F. C12A options in the C12MOR ($3FF1) are disabled. The C9A option register ($3FDF) is enabled, allowing software control over the IRQ sensitivity and the memory map configuration. The C9A COP reset register ($001D) and the C9A COP control register ($001E) are enabled, allowing software control over the C9A COP and clock monitor. The C12 COP clear register ($3FF0) is disabled. The port D data direction register ($0007) is enabled, allowing output capability on the seven port D pins.
* *
*
* *
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General Description Configuration Options
*
SPI output signals (MOSI, MISO, and SCK) require the corresponding bits in the port D data direction register to be set for output. The port D wire-OR mode control bit (bit 5 of SPCR $000A) is enabled, allowing open-drain configuration of port D. The RESET pin becomes bidirectional; this pin is driven low by a C9A COP or clock monitor timeout or during power-on reset.
* *
When configured as an MC68HC05C12A:
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* *
Memory locations $0100-$0FFF are disabled, creating a memory map identical to the MC68HC05C12A. C12A options in the C12MOR ($3FF1) are enabled; these bits control IRQ sensitivity, STOP instruction disable and C12 COP enable. The C9A option register ($3FDF) is disabled, preventing software control over the IRQ sensitivity and the memory map configuration. The C9A COP reset register ($001D) and the C9A COP control register ($001E) are disabled, preventing software control over the C9A COP and clock monitor. The C12 COP clear register ($3FF0) is enabled; this write-only register is used to clear the C12 COP. The port D data direction register ($0007) is disabled and the seven port D pins become input only. SPI output signals (MOSI, MISO, and SCK) do not require the data direction register control for output capability. The port D wire-OR mode control bit (bit 5 of SPCR $000A) is disabled, preventing open-drain configuration of port D. The RESET pin becomes input only.
*
*
* * * * *
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General Description 1.5 Mask Options
The following two mask option registers are used to select features controlled by mask changes on the MC68HC05C9A and the MC68HC05C12A: * * Port B mask option register (PBMOR) C12 mask option register (C12MOR)
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The mask option registers are EPROM locations which must be programmed prior to operation of the microcontroller.
1.5.1 Port B Mask Option Register (PBMOR) The PBMOR register, shown in Figure 1-2, contains eight programmable bits which determine whether each port B bit (when in input mode) has the pullup and interrupt enabled. The port B interrupts share the vector and edge/edge-level sensitivity with the IRQ pin. For more details, (see 4.4 External Interrupt (IRQ or Port B)).
$3FF0 Bit 7 PBPU7 6 PBPU6 5 PBPU5 4 PBPU4 3 PBPU3 2 PBPU2 1 PBPU1 Bit 0 PBPU0
Figure 1-2. Port B Mask Option Register PBPU7-PBPU0 -- Port B Pullup/Interrupt Enable Bits 1 = Pullup and CPU interrupt enabled 0 = Pullup and CPU interrupt disabled
NOTE:
The current capability of the port B pullup devices is equivalent to the MC68HC05C9A, which is less than the MC68HC05C12A.
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General Description Mask Options
1.5.2 C12 Mask Option Register (C12MOR) The C12MOR register, shown in Figure 1-3, controls the following options: * * * * Select between MC68HC05C9A/C12A configuration Enable/disable stop mode (C12A mode only) Enable/disable COP (C12A mode only) Edge-triggered only or edge- and level-triggered external interrupt pin (IRQ pin) (C12A mode only).
Bit 7 SEC Write: 6 5 4 3 C12COPE 2 STOPDIS 1 C12IRQ Bit 0 C12A
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$3FF1 Read:
= Unimplemented
Figure 1-3. Mask Option Register 2 C12A -- C12A/C9A Mode Select Bit This read/write bit selects between C12A configuration and C9A configuration. 1 = Configured to emulate MC68HC05C12A 0 = Configured to emulate MC68HC05C9A C12IRQ -- C12A Interrupt Request Bit This read/write bit selects between an edge-triggered only or edgeand level-triggered external interrupt pin. If configured in C9A mode, this bit has no effect and will be forced to 0 regardless of the programmed state. 1 = Edge and level interrupt option selected 0 = Edge-only interrupt option selected
NOTE:
Any Port B pin configured for interrupt capability will follow the same edge or edge/level trigger as the IRQ pin.
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General Description
STOPDIS -- STOP Instruction Disable Bit This read-only bit allows emulation of the "STOP disable" mask option on the MC68HC05C12A. (See 5.10 COP During Stop Mode.) If configured in MC68HC05C9A mode, this bit has no effect and will be forced to 0 regardless of the programmed state. 1 = If the MCU enters stop mode, the clock monitor is enabled to force a system reset 0 = STOP instruction executed as normal
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C12COPE -- C12A COP Enable Bit This read-only bit enables the COP function when configured in MC68HC05C12A mode. If configured in MC68HC05C9A mode, this bit has no effect and will be forced to 0 regardless of the programmed state. 1 = When in C12A mode, this enables the C12ACOP watchdog timer. 0 = When in C12A mode, this disables the C12ACOP watchdog timer. SEC -- Security Enable Bit This read-only bit enables the EPROM security feature. Once programmed, this bit helps to prevent external access to the programmed EPROM data. The EPROM data cannot be verified or modified. 1 = Security enabled 0 = Security disabled
NOTE:
During power-on reset, the device always will be configured as MC68HC05C9A regardless of the state of the C12A bit.
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General Description Software-Programmable Options (MC68HC05C9A Mode Only)
1.6 Software-Programmable Options (MC68HC05C9A Mode Only)
The C9A option register (OR), shown in Figure 1-4, is enabled only if configured in C9A mode. This register contains the programmable bits for the following options: * * Map two different areas of memory between RAM and EPROM, one of 48 bytes and one of 128 bytes Edge-triggered only or edge- and level-triggered external interrupt (IRQ pin and any port B pin configured for interrupt)
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This register must be written to by user software during operation of the microcontroller.
$3FDF Read: Write: Reset: 0 0 0 0 0 0 1 0 Bit 7 RAM0 6 RAM1 5 4 3 2 1 IRQ Bit 0
= Unimplemented
Figure 1-4. C9A Option Register RAM0 -- Random Access Memory Control Bit 0 This read/write bit selects between RAM or EPROM in location $0020 to $004F. This bit can be read or written at any time. 1 = RAM selected 0 = EPROM selected RAM1-- Random Access Memory Control Bit 1 This read/write bit selects between RAM or EPROM in location $0100 to $017F. This bit can be read or written at any time. 1 = RAM selected 0 = EPROM selected IRQ -- Interrupt Request Bit This bit selects between an edge-triggered only or edge- and leveltriggered external interrupt pin. This bit is set by reset, but can be cleared by software. This bit can be written only once. 1 = Edge and level interrupt option selected 0 = Edge-only interrupt option selected
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General Description 1.7 Functional Pin Descriptions
Figure 1-5, Figure 1-6, Figure 1-7, and Figure 1-8 show the pin assignments for the available packages. A functional description of the pins follows.
NOTE:
A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low.
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RESET IRQ VPP PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD OSC1 OSC2 TCAP PD7 TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
Figure 1-5. 40-Pin PDIP Pin Assignments
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Freescale Semiconductor, Inc.
General Description Functional Pin Descriptions
RESET IRQ VPP PA7 PA6 PA5 PA4 PA3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VDD OSC1 OSC2 TCAP PD7 TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 N/C PC3 PC4 PC5 PC6 PC7
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PA2 PA1 PA0 PB0 PB1 PB2 PB3 N/C PB4 PB5 PB6 PB7 VSS
Figure 1-6. 42-Pin SDIP Pin Assignments
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General Description
RESET
OSC1
OSC2
TCAP 41
44
43
42
PA5 PA4 PA3 PA2 PA1 PA0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1
40
6
5
4
3
2
PD7
PA6
PA7
VDD
IRQ
N/C
VPP
39 38 37 36 35 34 33 32 31 30 29
N/C TCMP PD5/SS PD4/SCK PD3/MOSI PD2MISO PD1/TDO PD0/RDI PC0 PC1 PC2
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PB0 PB1 PB2 PB3 N/C
23
24
25
26
27 PC4
PB4
PB5
PB6
PB7
N/C
PC7
PC6
PC5
Figure 1-7. 44-Lead PLCC Pin Assignments
NOTE:
The above 44-pin PLCC pin assignment diagram is for compatibility with MC68HC05C9A. To allow compatibility with the 44-pin PLCC MC68HC05C12A, pin17 and pin18 must be tied together and pin 39 and pin 40 also must be tied together. To allow compatibility with MC68HC705C8A, pin 3 and pin 4 also should be tied together.
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VSS
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PC3
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General Description Functional Pin Descriptions
RESET
OSC1
OSC2
TCAP 35
PA7
IRQ
VPP
N/C
44
43
42
41
40
39
N/C
38
37
36
PA6 PA5 PA4 PA3 PA2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
34
PD7
VDD
33 32 31 30 29 28 27 26 25 24 23
TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI PC0 PC1 PC2 PC3
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PA1 PA0 PB0 PB1 PB2 PB3
N/C
PB4
PB5
PB6
PB7
PC7
PC6
PC5
Figure 1-8. 44-Pin QFP Pin Assignments
1.7.1 VDD and VSS Power is supplied to the MCU using these two pins. VDD is the positive supply and VSS is ground.
1.7.2 VPP This pin provides the programming voltage to the EPROM array. For normal operation, VPP should be tied to VDD.
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VSS
PC4
N/C
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General Description
1.7.3 IRQ This interrupt pin has an option that provides two different choices of interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Section 4. Interrupts for more detail.
1.7.4 OSC1 andOSC2
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These pins provide control input for an on-chip clock oscillator circuit. A crystal connected to these pins provides a system clock. The internal frequency is one-half the crystal frequency.
1.7.5 RESET As an input pin, this active low RESET pin is used to reset the MCU to a known startup state by pulling RESET low. As an output pin, when in MC68HC05C9A mode only, the RESET pin indicates that an internal MCU reset has occurred. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Section 5. Resets for more detail.
1.7.6 TCAP This pin controls the input capture feature for the on-chip programmable timer. The TCAP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Section 8. Capture/Compare Timer for more detail.
1.7.7 TCMP The TCMP pin provides an output for the output compare feature of the on-chip programmable timer. Refer to Section 8. Capture/Compare Timer for more detail.
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General Description Functional Pin Descriptions
1.7.8 PA0-PA7 These eight I/O lines comprise port A. The state of each pin is software programmable and all port A pins are configured as inputs during reset. Refer to Section 7. Input/Output Ports for more detail.
1.7.9 PB0-PB7 These eight I/O lines comprise port B. The state of each pin is software programmable and all port B pins are configured as inputs during reset. Port B has mask option register enabled pullup devices and interrupt capability selectable for any pin. Refer to Section 7. Input/Output Ports for more detail.
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1.7.10 PC0-PC7 These eight I/O lines comprise port C. The state of each pin is software programmable and all port C pins are configured as inputs during reset. PC7 has high current sink and source capability. Refer to Section 7. Input/Output Ports for more detail.
1.7.11 PD0-PD5 and PD7 These seven I/O lines comprise port D. When configured as a C9A the state of each pin is software programmable and all port D pins are configured as inputs during reset. When configured as a C12A, the port D pins are input only. Refer to Section 7. Input/Output Ports for more detail.
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General Description
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MC68HC705C9A -- Rev. 4.0 MOTOROLA
Freescale Semiconductor, Inc.
Advance Information -- MC68HC705C9A
Section 2. Memory
2.1 Contents
2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 EPROM Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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2.3 2.4 2.5 2.6 2.7
2.2 Introduction
The MCU has a 16-Kbyte memory map when configured as either an MC68HC05C9A or an MC68HC05C12A. The memory map consists of registers (I/O, control, and status), user RAM, user EPROM, bootloader ROM, and reset and interrupt vectors as shown in Figure 2-1 and Figure 2-2. When configured as an MC68HC05C9A, two control bits in the option register ($3FDF) allow the user to switch between RAM and EPROM at any time in two special areas of the memory map, $0020-$004F (48 bytes) and $0100-$017F (128 bytes). When configured as an MC68HC05C12A, the section of the memory map from $0020 to $004F is fixed as EPROM and the section from $0100 to $0FFF becomes unused.
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Memory 2.3 RAM
The main user RAM consists of 176 bytes at $0050-$00FF. This RAM area is always present in the memory map and includes a 64-byte stack area. The stack pointer can access 64 bytes of RAM in the range $00FF down to $00C0.
NOTE:
Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. In MC68HC05C9A configuration, two additional RAM areas are available at $0020-$004F (48 bytes) and $0100-$017F (128 bytes) (see Figure 2-1 and Figure 2-2.) These may be accessed at any time by setting the RAM0 and RAM1 bits, respectively, in the C9A option register. Refer to 1.6 Software-Programmable Options (MC68HC05C9A Mode Only) for additional information.
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2.4 EPROM
When configured as a C12A the main user EPROM consists of 48 bytes of page zero EPROM from $0020 to $004F, 12,032 bytes of EPROM from $1000 to $3EFF, and 14 bytes of user vectors from $3FF4 to $3FFF. When configured as a C9A, an additional 3,840 bytes of user EPROM from $0100 to $0FFF are enabled. Locations $3FF0 and $3FF1 are the mask option registers (MOR) (see 1.5 Mask Options). For detailed information on programming the EPROM see Appendix A. EPROM Programming.
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Memory EPROM
$0000 I/O REGISTERS 32 BYTES $001F $0020 $004F $0050
USER EPROM 48 BYTES RAM0 = 0
RAM 48 BYTES RAM0 = 1
RAM 176 BYTES $00BF $00C0
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$00FF $0100
(STACK) 64 BYTES USER EPROM 128 BYTES RAM1 = 0 RAM 128 BYTES RAM1 = 1
$017F $0180
USER EPROM 15,744 BYTES
PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER PORT D DATA DIRECTION REGISTER UNUSED UNUSED SPI CONTROL REGISTER SPI STATUS REGISTER SPI DATA REGISTER SCI BAUD RATE REGISTER SCI CONTROL REGISTER 1 SCI CONTROL REGISTER 2 SCI STATUS REGISTER SCI DATA REGISTER TIMER CONTROL REGISTER TIMER STATUS REGISTER INPUT CAPTURE REGISTER (HIGH) INPUT CAPTURE REGISTER (LOW) OUTPUT COMPARE REGISTER (HIGH) OUTPUT COMPARE REGISTER (LOW) TIMER COUNTER REGISTER (HIGH) TIMER COUNTER REGISTER (LOW) ALTERNATE COUNTER REGISTER (HIGH) ALTERNATE COUNTER REGISTER (LOW) UNUSED COP RESET REGISTER COP CONTROL REGISTER UNUSED
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$3EFF $3F00
PORT B MASK OPTION REGISTER MASK OPTION REGISTER 2 UNUSED (2 BYTES) BOOTLOADER ROM AND VECTORS 239 BYTES SPI VECTOR (HIGH) SPI VECTOR (LOW) SCI VECTOR (HIGH) SCI VECTOR (LOW) TIMER VECTOR (HIGH) TIMER VECTOR (LOW) IRQ VECTOR (HIGH) IRQ VECTOR (LOW) SWI VECTOR (HIGH) SWI VECTOR (LOW) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE)
$3FDF C9A OPTION REGISTER $3FEF $3FF0 $3FF1 MASK OPTION REGISTERS $3FF2 USER EPROM VECTORS 14 BYTES $3FFF
$3FF0 $3FF1 $3FF2 $3FF3 $3FF4 $3FF5 $3FF6 $3FF7 $3FF8 $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF
Figure 2-1. C9A Memory Map
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Memory
$0000 I/O REGISTERS 32 BYTES $001F $0020 USER EPROM 48 BYTES $004F $0050 RAM 176 BYTES $00BF $00C0
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(STACK) 64 BYTES $00FF $0100 UNUSED 3840 BYTES $0FFF $1000
USER EPROM 12,032 BYTES
PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER UNUSED UNUSED UNUSED SPI CONTROL REGISTER SPI STATUS REGISTER SPI DATA REGISTER SCI BAUD RATE REGISTER SCI CONTROL REGISTER 1 SCI CONTROL REGISTER 2 SCI STATUS REGISTER SCI DATA REGISTER TIMER CONTROL REGISTER TIMER STATUS REGISTER INPUT CAPTURE REGISTER (HIGH) INPUT CAPTURE REGISTER (LOW) OUTPUT COMPARE REGISTER (HIGH) OUTPUT COMPARE REGISTER (LOW) TIMER COUNTER REGISTER (HIGH) TIMER COUNTER REGISTER (LOW) ALTERNATE COUNTER REGISTER (HIGH) ALTERNATE COUNTER REGISTER (LOW) UNUSED UNUSED UNUSED UNUSED
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
$3EFF $3F00
MASK OPTION REGISTER/C12 COP REGISTER MASK OPTION REGISTER UNUSED UNUSED BOOTLOADER ROM AND VECTORS 240 BYTES SPI VECTOR (HIGH) SPI VECTOR (LOW) SCI VECTOR (HIGH) SCI VECTOR (LOW) TIMER VECTOR (HIGH) TIMER VECTOR (LOW) IRQ VECTOR (HIGH) IRQ VECTOR (LOW) SWI VECTOR (HIGH) SWI VECTOR (LOW) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE)
$3FEF $3FF0 $3FF1 $3FF2 $3FFF
MASK OPTION REGISTERS USER EPROM VECTORS 14 BYTES
$3FF0 $3FF1 $3FF2 $3FF3 $3FF4 $3FF5 $3FF6 $3FF7 $3FF8 $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF
Figure 2-2. C12A Memory Map
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Memory EPROM Security
2.5 EPROM Security
A security feature has been incorporated into the MC68HC705C9A to help prevent external access to the contents of the EPROM in any mode of operation. Once enabled, this feature can be disabled only by completely erasing the EPROM.
NOTE:
For OTP (plastic) packages, once the security feature has been enabled, it cannot be disabled.
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2.6 ROM
The bootloader ROM occupies 239 bytes in the memory space from $3F00 to $3FEF. The bootloader mode provides for self-programming of the EPROM array. See Appendix A. EPROM Programming.
2.7 I/O Registers
Except for the option register, mask option registers, and the C12 COP clear register, all I/O, control and status registers are located within one 32-byte block in page zero of the address space ($0000-$001F). A summary of these registers is shown in Figure 2-3. More detail about the contents of these registers is given Figure 2-4.
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Memory
Addr $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007
Register Name Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register (C9A Only) Unused Unused Serial Peripheral Control Register Serial Peripheral Status Register Serial Peripheral Data Register Baud Rate Register Serial Communications Control Register 1 Serial Communications Control Register 2 Serial Communications Status Register Serial Communications Data Register Timer Control Register Timer Status Register Input Capture Register High Input Capture Register Low Output Compare Register High Output Compare Register Low Timer Register High Timer Register Low Alternate Timer Register High Alternate Timer Register Low EPROM Programming Register C9A COP Reset Register C9A COP Control Register Reserved
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$0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
Figure 2-3. I/O Register Summary
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Memory I/O Registers
Addr.
Register Name Read: Port A Data Register (PORTA) Write: See page 69. Reset: Read: Port B Data Register (PORTB) Write: See page 70. Reset: Read: Port C Data Register (PORTC) Write: See page 71. Reset: Read: Port D Data Register (PORTD) Write: See page 71. Reset:
Bit 7 PA7
6 PA6
5 PA5
4 PA4
3 PA3
2 PA2
1 PA1
Bit 0 PA0
$0000
Unaffected by reset PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
$0001
Unaffected by reset PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
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$0002
Unaffected by reset PD7 PD5 PD4 PD3 PD2 PD1 PD0
$0003
Unaffected by reset DDRA6 0 DDRB6 0 DDRA5 0 DDRB5 0 DDRC5 0 DDRC5 0 0 DDRA4 0 DDRB4 0 DDRC4 0 DDRC4 0 DDRA3 0 DDRB3 0 DDRC3 0 DDRC3 0 DDRA2 0 DDRB2 0 DDRC2 0 DDRC2 0 DDRA1 0 DDRB1 0 DDRC1 0 DDRC1 0 DDRA0 0 DDRB0 0 DDRC0 0 DDRC0 0
Read: Port A Data Direction Register DDRA7 $0004 (DDRA) Write: See page 69. Reset: 0 Read: Port B Data Direction Register DDRB7 $0005 (DDRB) Write: See page 70. Reset: 0
Read: Port C Data Direction Register DDRC7 DDRC6 $0006 (DDRC) Write: See page 71. Reset: 0 0 Read: Port D Data Direction Register DDRC7 $0007 (DDRD) C9A Only Write: See page 71. Reset: 0 $0008 Unimplemented
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-4. Input/Output Registers (Sheet 1 of 4)
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Memory
Addr. $0009
Register Name Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
$000A
Read: SPI Control Register (SPCR) Write: See page 109. Reset: Read: SPI Status Register (SPSR) Write: See page 111. Reset:
SPIE 0 SPIF
SPE 0 WCOL
DWOM (C9A) 0
MSTR 0 MODF
CPOL 0
CPHA 1
SPR1 U
SPR0 U
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$000B
0
0 SPD6
0 SPD5
0 SPD4
0 SPD3
0 SPD2
0 SPD1
0 SPD0
$000C
Read: SPI Data Register SPD7 (SPDR) Write: See page 113. Reset: Read: SCI Baud Rate Register BAUD Write: See page 101. Reset: Read: SCI Control Register 1 (SCCR1) Write: See page 95. Reset: Read: SCI Control Register 2 (SCCR2) Write: See page 96. Reset:
Unaffected by reset SCP1 SCP0 0 M 0 RIE 0 RDRF U ILIE 0 IDLE -- WAKE U TE 0 OR 0 RE 0 NF 0 RWU 0 FE 0 SBK 0 SCR2 U SCR1 U SCR0 U
$000D
-- R8 U TIE 0
-- T8 U TCIE 0 TC
0
$000E
$000F
$0010
Read: TDRE SCI Status Register (SCSR) Write: See page 99. Reset: 1 Read: SCI Data Register SCD7 (SCDR) Write: See page 94. Reset:
1 SDC6
0 SCD5
0 SCD4
0 SCD3
0 SCD2
0 SCD1
-- SCD0
$0011
Unaffected by reset = Unimplemented R = Reserved U = Unaffected
Figure 2-4. Input/Output Registers (Sheet 2 of 4)
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Memory I/O Registers
Addr.
Register Name Read: Timer Control Register (TCR) Write: See page 76. Reset: Read: Timer Status Register (TSR) Write: See page 78. Reset:
Bit 7 ICIE 0 ICF
6 OCIE 0 OCF
5 TOIE 0 TOF
4 0
3 0
2 0
1 IEDG
Bit 0 OLVL 0 0
$0012
0 0
0 0
0 0
U 0
$0013
U
U Bit 14
U Bit 13
0 Bit 12
0 Bit 11
0 Bit 10
0 Bit 9
0 Bit 8
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$0014
Read: Bit 15 Input Capture Register High (ICRH) Write: See page 81. Reset: Read: Input Capture Register Low (ICRL) Write: See page 81. Reset: Bit 7
Unaffected by reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0015
Unaffected by reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0016
Read: Output Compare Register Bit 15 High (OCRH) Write: See page 82. Reset: Read: Output Compare Register Low (OCRL) Write: See page 82. Reset: Bit 7
Unaffected by reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0017
Unaffected by reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$0018
Read: Bit 15 Timer Register High (TRH) Write: See page 79. Reset: 1 Timer Register Low Read: (TRL) Write: See page 79. Reset: Bit 7
1 Bit 6
1 Bit 5
1 Bit 4
1 Bit 3
1 Bit 2
1 Bit 1
1 Bit 0
$0019
1
1 Bit 14
1 Bit 13
1 Bit 12
1 Bit 11
1 Bit 10
0 Bit 9
0 Bit 8
$001A
Read: Bit 15 Alternate Timer Register High (ATRH) Write: See page 80. Reset: 1
1
1
1 R
1 = Reserved
1
1
1
= Unimplemented
U = Unaffected
Figure 2-4. Input/Output Registers (Sheet 3 of 4)
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Memory
Addr.
Register Name Read: Alternate Timer Register Low (ATRL) Write: See page 80. Reset: Read: EPROM Programming Register (EPR) Write: Reset:
Bit 7 Bit 7
6 Bit 6
5 Bit 5
4 Bit 4
3 Bit 3
2 Bit 2
1 Bit 1
Bit 0 Bit 0
$001B
1
1
1
1
1
1 LATCH
0
0 EPGM
$001C
0
0
0
0
0
0
0
0
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$001D
Read: COP Reset Register (COPRST) C9A Only Write: See page 61. Reset: Read: COP Control Register (COPCR) C9A Only Write: See page 62. Reset: Reserved
Bit 7 0 0
Bit 6 0 0
Bit 5 0 0
Bit 4 0 COPF
Bit 3 0 CME 0 R
Bit 2 0 COPE 0 R
Bit 1 0 CM1 0 R
Bit 0 0 CM0 0 R
$001E
0 R
0 R
0 R
U R
$001F
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-4. Input/Output Registers (Sheet 4 of 4)
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Advance Information -- MC68HC705C9A
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.2 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.3 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.3.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.5 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 49
3.2 Introduction
This section contains the basic programmers model and the registers contained in the CPU.
3.3 CPU Registers
The MCU contains five registers as shown in the programming model of Figure 3-1. The interrupt stacking order is shown in Figure 3-2.
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Central Processor Unit (CPU)
7 A 7 X 15 PC 15 0 0 0 0 0 0 0 0 7 1 1 SP CCR
0 ACCUMULATOR 0 INDEX REGISTER 0 PROGRAM COUNTER 0 STACK POINTER
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H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1 0 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL UNSTACK
STACK I N T E R R U P T
DECREASING MEMORY ADDRESSES
Figure 3-2. Interrupt Stacking Order
3.3.1 Accumulator (A) The accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.
3.3.2 Index Register (X) The index register is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area.
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Central Processor Unit (CPU) CPU Registers
3.3.3 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next byte to be fetched.
3.3.4 Stack Pointer (SP) The stack pointer contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $0FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the eight most significant bits are permanently set to 00000011. These eight bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
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3.3.5 Condition Code Register (CCR) The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer, SCI, SPI, and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared.
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Central Processor Unit (CPU)
Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/Borrow (C)
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When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.
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Section 4. Interrupts
4.1 Contents
4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Non-Maskable Software Interrupt (SWI). . . . . . . . . . . . . . . . . . 53 External Interrupt (IRQ or Port B) . . . . . . . . . . . . . . . . . . . . . . . 53 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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4.3 4.4 4.5 4.6 4.7
4.2 Introduction
The MCU can be interrupted by five different sources, four maskable hardware interrupts, and one non-maskable software interrupt: * * * * * External signal on the IRQ pin or port B pins 16-bit programmable timer Serial communications interface Serial peripheral interface Software interrupt instruction (SWI)
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete.
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Interrupts
NOTE:
The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear) and if the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If an external interrupt and a timer, SCI, or SPI interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. Table 4-1 shows the relative priority of all the possible interrupt sources. Figure 4-1 shows the interrupt processing flow.
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Table 4-1. Vector Addresses for Interrupts and Resets
Function Source Power-on reset Reset RESET pin COP watchdog Software interrupt (SWI) External interrupt Timer interrupts User code None None Same priority as instruction 2 $3FFC-$3FFD None None 1 $3FFE-$3FFF Local Mask Global Mask Priority (1 = Highest) Vector Address
IRQ pin port B pins ICF bit OCF bit TOF bit TDRE bit TC bit
None ICIE bit OCIE bit TOIE bit TCIE bit
I bit
$3FFA-$3FFB
I bit
3
$3FF8-$3FF9
SCI interrupts
RDRF bit OR bit IDLE bit RIE bit ILIE bit SPIE
I bit
4
$3FF6-$3FF7
SPI interrupts
SPIF bit MODF bit I bit 5 $3FF4-$3FF5
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Interrupts Non-Maskable Software Interrupt (SWI)
4.3 Non-Maskable Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt: It is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI executes after interrupts which were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.
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4.4 External Interrupt (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of IRQ. It is then synchronized internally and serviced as specified by the contents of $3FFA and $3FFB. When any of the port B pullups are enabled, each pin becomes an additional external interrupt source which is executed identically to the IRQ pin. Port B interrupts follow the same edge/edge-level selection as the IRQ pin. The branch instructions BIL and BIH also respond to the port B interrupts in the same way as the IRQ pin. See 7.4 Port B. Either a level-sensitive and edge-sensitive trigger or an edge-sensitiveonly trigger operation is selectable. In MC68HC05C9A mode, the sensitivity is software controlled by the IRQ bit in the C9A option register ($3FDF). In the MC68HC05C12A mode, the sensitivity is determined by the C12IRQ bit in the C12 mask option register ($3FF1).
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse can be latched and serviced as soon as the I bit is cleared.
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Interrupts 4.5 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF8 and $3FF9.
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4.6 SCI Interrupt
Five different SCI interrupt flags cause an SCI interrupt whenever they are set and enabled. The interrupt flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2). Any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF6 and $3FF7.
4.7 SPI Interrupt
Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF4 and $3FF5.
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Interrupts SPI Interrupt
FROM RESET
Y
I BIT IN CCR SET? N IRQ OR PORT B EXTERNAL INTERRUPT CLEAR IRQ REQUEST LATCH
Y
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N INTERNAL TIMER INTERRUPT N INTERNAL SCI INTERRUPT N INTERNAL SPI INTERRUPT N
Y
Y
Y
STACK PC,X,A,CCR
FETCH NEXT INSTRUCTION
SET I BIT IN CC REGISTER
SWI INSTRUCTION ? N
LOAD PC FROM: Y SWI: $3FFC-$3FFD IRQ: $3FFA-$3FFB TIMER: $3FF8-$3FF9 SCI: $3FF6-$3FF7 SPI: $3FF4-$3FF5
Y
RTI INSTRUCTION ? N
RESTORE REGISTERS FROM STACK: CCR,A,X,PC
EXECUTE INSTRUCTION
Figure 4-1. Interrupt Flowchart
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Interrupts
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Section 5. Resets
5.1 Contents
5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .60
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5.3 5.4 5.5
5.6 MC68HC05C9A Compatible COP . . . . . . . . . . . . . . . . . . . . . . 60 5.6.1 C9A COP Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.6.2 C9A COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.7 5.8 5.9 MC68HC05C12A Compatible COP . . . . . . . . . . . . . . . . . . . . . 63 MC68HC05C12A Compatible COP Clear Register . . . . . . . . . 64 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.10 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.10.1 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.10.2 STOP Instruction Disable Option . . . . . . . . . . . . . . . . . . . . . 65
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Resets 5.2 Introduction
The MCU can be reset four ways: by the initial power-on reset function, by an active low input to the RESET pin, by the COP, or by the clock monitor. A reset immediately stops the operation of the instruction being executed, initializes some control bits, and loads the program counter with a user-defined reset vector address. Figure 5-1 is a block diagram of the reset sources.
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CLOCK MONITOR
COP WATCHDOG
VDD
POWER-ON RESET STOP
RESET
R D Q RESET LATCH INTERNAL CLOCK
RST
TO CPU AND SUBSYSTEMS
Figure 5-1. Reset Sources
5.3 Power-On Reset (POR)
A power-on-reset occurs when a positive transition is detected on VDD. The power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a 4064 internal processor clock cycle (tcyc) oscillator stabilization delay after the oscillator becomes active. (When configured as a C9A, the RESET pin will output a logic 0 during the 4064-cycle delay.) If the RESET pin is low after the end of this 4064-cycle delay, the MCU will remain in the reset condition until RESET is driven high externally.
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Resets RESET Pin
5.4 RESET Pin
The function of the RESET pin is dependent on whether the device is configured as an MC68HC05C9A or an MC68HC05C12A. When it is in the MC68HC05C12A configuration, the pin is input only. When in MC68HC05C9A configuration the pin is bidirectional. In both cases the MCU is reset when a logic 0 is applied to the RESET pin for a period of one and one-half machine cycles (tRL). For the MC68HC05C9A configuration, the RESET pin will be driven low by a COP, clock monitor, or power-on reset.
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VDD
t VDDR
OSC12
4064tCYC t CYC INTERNAL CLOCK1 INTERNAL ADDRESS BUS1 INTERNAL DATA BUS1
3FFE
3FFF
NEW PC
DUMMY
NEW PC
OP CODE
3FFE
3FFE
3FFE
3FFE
3FFF
NEW PC
DUMMY
NEW PC
OP CODe
NEW PCH
NEW PCL
PCH
PCL
RESET (C9A)
t RL 4 3
RESET (C12A)
t RL 3
Notes: 1. Internal timing signal and bus information are not available externally. 2. OSC1 line is not meant to represent frequency. It is only meant to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. 4. RESET outputs VOL during 4064 power-on reset cycles when in C9A mode only.
Figure 5-2. Power-On Reset and RESET
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Resets 5.5 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature which guards against program run-away failures. A timeout of the computer operating properly (COP) timer generates a COP reset. The COP watchdog is a software error detection system that automatically times out and resets the MCU if not cleared periodically by a program sequence. This device includes two COP types, one for C12A compatibility and the other for C9A compatibility. When configured as a C9A the COP can be enabled by user software by setting COPE in the C9A COP control register (C9ACOPCR). When configured as a C12A, the COP is enabled prior to operation by programming the C12COPE bit in the C12A mask option register (C12MOR). The function and control of both COPs is detailed below.
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5.6 MC68HC05C9A Compatible COP
This COP is controlled with two registers; one to reset the COP timer and the other to enable and control COP and clock monitor functions. Figure 5-3 shows a block diagram of the MC68HC05C9A COP.
CM1 INTERNAL CPU CLOCK /4 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 CM0
16 BIT TIMER SYSTEM 213
215 217 219 /4 /2 /2 /2 /2 /2 /2 221 COP
COPRST
Figure 5-3. C9A COP Block Diagram
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Resets MC68HC05C9A Compatible COP
5.6.1 C9A COP Reset Register This write-only register, shown in Figure 5-4, is used to reset the COP.
$001D Read: Write: Reset: Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented
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Figure 5-4. COP Reset Register (COPRST) The sequence required to reset the COP timer is: * * Write $55 to the COP reset register Write $AA to the COP reset register
Both write operations must occur in the order listed, but any number of instructions may be executed between the two write operations provided that the COP does not time out between the two writes. The elapsed time between software resets must not be greater than the COP timeout period. If the COP should time out, a system reset will occur and the device will be re-initialized in the same fashion as a power-on reset or reset. Reading this register does not return valid data.
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Resets
5.6.2 C9A COP Control Register The COP control register, shown in Figure 5-5, performs these functions: * * * Enables clock monitor function Enables MC68HC05C9A compatible COP function Selects timeout duration of COP timer
and flags the following conditions:
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* *
$001E Read: Write: Reset:
A COP timeout Clock monitor reset
Bit 7 0 6 0 5 0 COPF 0 0 0 U CME 0 COPE 0 CM1 0 CM0 0 4 3 2 1 Bit 0
= Unimplemented
U = Undetermined
Figure 5-5. COP Control Register (COPCR) COPF -- Computer Operating Properly Flag Reading the COP control register clears COPF. 1 = COP or clock monitor reset has occurred. 0 = No COP or clock monitor reset has occurred. CME -- Clock Monitor Enable Bit This bit is readable any time, but may be written only once. 1 = Clock monitor enabled 0 = Clock monitor disabled COPE -- COP Enable Bit This bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by reset. 1 = COP enabled 0 = COP disabled
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Resets MC68HC05C12A Compatible COP
CM1 -- COP Mode Bit 1 Used in conjunction with CM0 to establish the COP timeout period, this bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by reset. CM0 -- COP Mode Bit 0 Used in conjunction with CM1 to establish the COP timeout period, this bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by reset. Bits 7-5 -- Not Used These bits always read as 0. Table 5-1. COP Timeout Period
CM1 0 0 1 1 CM0 0 1 0 1 fop/215 Divide By 1 4 16 64 Timeout Period (fosc = 2.0 MHz) 32.77 ms 131.07 ms 524.29 ms 2.097 sec Timeout Period (fosc = 4.0 MHz) 16.38 ms 65.54 ms 262.14 ms 1.048 sec
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5.7 MC68HC05C12A Compatible COP
This COP is implemented with an 18-bit ripple counter. This provides a timeout period of 64 milliseconds at a bus rate (fop) of 2 MHz. If the COP should time out, a system reset will occur and the device will be reinitialized in the same fashion as a power-on reset or reset.
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Resets 5.8 MC68HC05C12A Compatible COP Clear Register
The COP clear register, shown in Figure 5-6, resets the C12A COP counter.
$3FF0 Read: Write: Reset: 0 0 0 U 0 0 0 COPC 0 Bit 7 6 5 4 3 2 1 Bit 0
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= Unimplemented
U = Undetermined
Figure 5-6. COP Clear Register (COPCLR) COPC -- Computer Operating Properly Clear Bit Preventing a COP reset is achieved by writing a 0 to the COPC bit. This action will reset the counter and begin the timeout period again. The COPC bit is bit 0 of address $3FF0. A read of address $3FF0 will result in the data programmed into the mask option register PBMOR.
5.9 COP During Wait Mode
Either COP will continue to operate normally during wait mode. The software must pull the device out of wait mode periodically and reset the COP to prevent a system reset.
5.10 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will be reset after the 4064 cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program.
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Resets COP During Stop Mode
In the event that an inadvertent STOP instruction is executed, neither COP will allow the system to recover. The MC68HC705C9A offers two solutions to this problem, one available in C9A mode (see 5.10.1 Clock Monitor Reset) and one available in C12A mode (see 5.10.2 STOP Instruction Disable Option).
5.10.1 Clock Monitor Reset When configured as a C9A, the clock monitor circuit can provide a system reset if the clock stops for any reason, including stop mode. When the CME bit in the C9A COP control register is set, the clock monitor detects the absence of the internal bus clock for a certain period of time. The timeout period is dependent on the processing parameters and varies from 5 s to 100 s, which implies that systems using a bus clock rate of 200 kHz or less should not use the clock monitor. If a slow or absent clock is detected, the clock monitor causes a system reset. The reset is issued to the external system via the bidirectional RESET pin for four bus cycles if the clock is slow or until the clocks recover in the case where the clocks are absent.
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5.10.2 STOP Instruction Disable Option On the ROM device MC68HC05C12A, stop mode can be disabled by mask option. This causes the CPU to interpret the STOP instruction as a NOP so the device will never enter stop mode; if the user code is not being executed properly, the COP will provide a system reset. To emulate this feature on the MC68HC705C9A (configured as an MC68HC05C12A), set the STOPDIS bit in the C12MOR. Stop mode will not actually be disabled as on the MC68HC05C12A, but the clock monitor circuit will be activated. If the CPU executes a STOP instruction, the clock monitor will provide a system reset.
NOTE:
This feature cannot be used with operating frequencies of 200 kHz or less.
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Resets
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Section 6. Low-Power Modes
6.1 Contents
6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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6.3 6.4
6.2 Introduction
This section describes the low-power modes.
6.3 Stop Mode
The STOP instruction places the MCU in its lowest-power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. During the stop mode, the TCR bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit in the CCR is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the stop mode only by an external interrupt or reset. See Figure 6-1.
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Low-Power Modes
(1) OSC1 tRL RESET
IRQ
(2)
t
LIH
IRQ
(3)
t
ILCH
4064 t
cyc
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INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option
3FFE
3FFE
3FFE
3FFE
3FFF
RESET OR INTERRUPT VECTOR FETCH
Figure 6-1. Stop Recovery Timing Diagram
6.4 Wait Mode
The WAIT instruction places the MCU in a low-power consumption mode, but the wait mode consumes more power than the stop mode. All CPU action is suspended, but the timer, serial communications interface (SCI), serial peripheral interface (SPI), and the oscillator remain active. Any interrupt or reset will cause the MCU to exit the wait mode. During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The timer, SCI, and SPI may be enabled to allow a periodic exit from the wait mode.
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Section 7. Input/Output (I/O) Ports
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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7.3 7.4 7.5 7.6
7.2 Introduction
This section briefly describes the 31 input/output (I/O) lines arranged as one 7-bit and three 8-bit ports. All of these port pins are programmable as either inputs or outputs under software control of the data direction registers.
NOTE:
To avoid a glitch on the output pins, write data to the I/O port data register before writing a one to the corresponding data direction register.
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. The contents of the port A data register are indeterminate at initial powerup and must be initialized by user software. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. A block diagram of the port logic is shown in Figure 7-1.
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Input/Output (I/O) Ports
DATA DIRECTION REGISTER BIT
INTERNAL HC05 CONNECTIONS
LATCHED OUTPUT DATA BIT
I/O OUTPUT PIN
INPUT REG BIT
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INPUT I/O
Figure 7-1. Port A I/O Circuit
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register (DDR) is at $0005. The contents of the port B data register are indeterminate at initial powerup and must be initialized by user software. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port pin to output mode. Each of the port B pins has an optional external interrupt capability that can be enabled by programming the corresponding bit in the port B mask option register ($3FF0). The interrupt option also enables a pullup device when the pin is configured as an input. The edge or edge- and level-sensitivity of the IRQ pin will also pertain to the enabled port B pins. Care needs to be taken when using port B pins that have the pullup enabled. Before switching from an output to an input, the data should be preconditioned to a 1 to prevent an interrupt from occurring. The port B logic is shown in Figure 7-2.
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Input/Output (I/O) Ports Port C
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register (DDR) is at $0006. The contents of the port C data register are indeterminate at initial powerup and must be initialized by user software. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. PC7 has a high current sink and source capability. Figure 7-1 is also applicable to port C.
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7.6 Port D
When configured as a C9A, port D is a 7-bit bidirectional port; when configured as a C12A, port D is a 7-bit fixed input port. Four of its pins are shared with the SPI subsystem and two more are shared with the SCI subsystem. The contents of the port D data register are indeterminate at initial powerup and must be initialized by user software. During reset all seven bits become valid input ports because the C9A DDR bits are cleared and the special function output drivers associated with the SCI and SPI subsystems are disabled, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode only when configured as a C9A.
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Input/Output (I/O) Ports
VDD DISABLED PORT B EXTERNAL INTERRUPT MASK OPTION REGISTER CONTROLLED ENABLED READ $0005 WRITE $0005 INTERNAL DATA BUS RESET
VDD
DATA DIRECTION REGISTER B BIT DDRB7 PORT B DATA REGISTER BIT PB7
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WRITE $0001
PBX
READ $0001
SOFTWARE OR MASK OPTION REGISTER CONTROLLED DEPENDENT ON CONFIGURATION EDGE AND LEVEL
EDGE ONLY
VDD D FROM OTHER PORT B PINS Q EXTERNAL INTERRUPT REQUEST I BIT (FROM CCR) IRQ
C
R
Q
RESET EXTERNAL INTERRUPT VECTOR FETCH
Figure 7-2. Port B I/O Logic
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Section 8. Capture/Compare Timer
8.1 Content
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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8.3 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.3.1 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.3.2 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 8.4 Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 8.4.1 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 8.4.2 Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.4.3 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.4.4 Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.4.5 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.4.6 Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.5 8.6 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.2 Introduction
This section describes the operation of the 16-bit capture/compare timer. Figure 8-1 shows the structure of the capture/compare subsystem.
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Capture/Compare Timer
INTERNAL BUS INTERNAL PROCESSOR CLOCK $16 $17 OUTPUT COMPARE REGISTER /4 HIGH BYTE 16-BIT FREE RUNNING COUNTER LOW BYTE $18 $19 HIGH LOW BYTE BYTE INPUT $14 CAPTURE $15 REGISTER
HIGH BYTE
LOW BYTE
8-BIT BUFFER
COUNTER $1A ALTERNATE $1B REGISTER
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OUTPUT COMPARE CIRCUIT
OVERFLOW DETECT CIRCUIT
EDGE DETECT CIRCUIT DQ CLK C
TIMER STATUS ICF OCF TOF $13 REG.
OUTPUT LEVEL REG.
TIMER CONTROLRESET ICIE OCIE TOIE IEDG OLVL REG. $12 INTERRUPT CIRCUIT OUTPUT LEVEL (TCMP) EDGE INPUT (TCAP)
Figure 8-1. Capture/Compare Timer Block Diagram
8.3 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter. The counter provides the timing reference for the input capture and output compare functions. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. Software can read the value in the 16-bit free-running counter at any time without affecting the counter sequence. Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare functions are pairs of 8-bit registers.
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Capture/Compare Timer Timer Operation
Because the counter is 16 bits long and preceded by a fixed divide-by-4 prescaler, the counter rolls over every 262,144 internal clock cycles. Timer resolution with a 4-MHz crystal is 2 s.
8.3.1 Input Capture The input capture function is a means to record the time at which an external event occurs. When the input capture circuitry detects an active edge on the TCAP pin, it latches the contents of the timer registers into the input capture registers. The polarity of the active edge is programmable. Latching values into the input capture registers at successive edges of the same polarity measures the period of the input signal on the TCAP pin. Latching values into the input capture registers at successive edges of opposite polarity measures the pulse width of the signal.
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8.3.2 Output Compare The output compare function is a means of generating an output signal when the 16-bit counter reaches a selected value. Software writes the selected value into the output compare registers. On every fourth internal clock cycle the output compare circuitry compares the value of the counter to the value written in the output compare registers. When a match occurs, the timer transfers the programmable output level bit (OLVL) from the timer control register to the TCMP pin. The programmer can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the TCMP pin.
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Capture/Compare Timer 8.4 Timer I/O Registers
The following I/O registers control and monitor timer operation: * * * * Timer control register (TCR) Timer status register (TSR) Timer registers (TRH and TRL) Alternate timer registers (ATRH and ATRL) Input capture registers (ICRH and ICRL) Output compare registers (OCRH and OCRL)
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* *
8.4.1 Timer Control Register The timer control register (TCR), shown in Figure 8-2, performs these functions: * * * * *
$0012 Read: ICIE Write: Reset: 0 0 0 0 0 0 U 0 OCIE TOIE
Enables input capture interrupts Enables output compare interrupts Enables timer overflow interrupts Controls the active edge polarity of the TCAP signal Controls the active level of the TCMP output
Bit 7 6 5 4 0 3 0 2 0 IEDG OLVL 1 Bit 0
= Unimplemented
U = Undetermined
Figure 8-2. Timer Control Register (TCR)
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Capture/Compare Timer Timer I/O Registers
ICIE -- Input Capture Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCAP pin. Resets clear the ICIE bit. 1 = Input capture interrupts enabled 0 = Input capture interrupts disabled OCIE -- Output Compare Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCMP pin. Resets clear the OCIE bit. 1 = Output compare interrupts enabled 0 = Output compare interrupts disabled TOIE -- Timer Overflow Interrupt Enable Bit This read/write bit enables interrupts caused by a timer overflow. Reset clear the TOIE bit. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled IEDG -- Input Edge Bit The state of this read/write bit determines whether a positive or negative transition on the TCAP pin triggers a transfer of the contents of the timer register to the input capture register. Resets have no effect on the IEDG bit. 1 = Positive edge (low to high transition) triggers input capture 0 = Negative edge (high to low transition) triggers input capture OLVL -- Output Level Bit The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when a successful output compare occurs. Resets clear the OLVL bit. 1 = TCMP goes high on output compare 0 = TCMP goes low on output compare
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Capture/Compare Timer
8.4.2 Timer Status Register The timer status register (TSR), shown in Figure 8-3, contains flags to signal the following conditions: * * *
$0013 Read: Write: Reset: U U U 0 0 0 0 0
An active signal on the TCAP pin, transferring the contents of the timer registers to the input capture registers A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to the TCMP pin A timer roll over from $FFFF to $0000
Bit 7 ICF 6 OCF 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0
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= Unimplemented
U = Undetermined
Figure 8-3. Timer Status Register (TSR) ICF -- Input Capture Flag The ICF bit is set automatically when an edge of the selected polarity occurs on the TCAP pin. Clear the ICF bit by reading the timer status register with ICF set and then reading the low byte ($0015) of the input capture registers. Resets have no effect on ICF. OCF -- Output Compare Flag The OCF bit is set automatically when the value of the timer registers matches the contents of the output compare registers. Clear the OCF bit by reading the timer status register with OCF set and then reading the low byte ($0017) of the output compare registers. Resets have no effect on OCF. TOF -- Timer Overflow Flag The TOF bit is set automatically when the 16-bit counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with TOF set, and then reading the low byte ($0019) of the timer registers. Resets have no effect on TOF.
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Capture/Compare Timer Timer I/O Registers
8.4.3 Timer Registers The timer registers (TRH and TRL), shown in Figure 8-4, contains the current high and low bytes of the 16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer registers has no effect.
TRH $0018
Bit 7 Bit 15
6 Bit 14
5 Bit 13
4 Bit 12
3 Bit 11
2 Bit 10
1 Bit 9
Bit 0 Bit 8
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Read: Write Reset:
1
1
1
1
1
1
1
1
TRL $0019 Read: Write: Reset:
Bit 7 Bit 7
6 Bit 6
5 Bit 5
4 Bit 4
3 Bit 3
2 Bit 2
1 Bit 1
Bit 0 Bit 0
1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-4. Timer Registers (TRH and TRL)
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Capture/Compare Timer
8.4.4 Alternate Timer Registers The alternate timer registers (ATRH and ATRL), shown in Figure 8-5, contain the current high and low bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL is read. Reading ATRL has no effect on the timer overflow flag (TOF). Writing to the alternate timer registers has no effect.
ATRH $001A
Bit 7 Bit 15
6 Bit 14
5 Bit 13
4 Bit 12
3 Bit 11
2 Bit 10
1 Bit 9
Bit 0 Bit 8
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Read: Write: Reset:
1
1
1
1
1
1
1
1
ATRL $001B Read: Write: Reset:
Bit 7 Bit 7
6 Bit 6
5 Bit 5
4 Bit 4
3 Bit 3
2 Bit 2
1 Bit 1
Bit 0 Bit 0
1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
NOTE:
To prevent interrupts from occurring between readings of ATRH and ATRL, set the interrupt flag in the condition code register before reading ATRH, and clear the flag after reading ATRL.
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Capture/Compare Timer Timer I/O Registers
8.4.5 Input Capture Registers When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are latched into the input capture registers (ICRH and ICRL). Reading ICRH before reading ICRL inhibits further capture until ICRL is read. Reading ICRL after reading the status register clears the input capture flag (ICF). Writing to the input capture registers has no effect.
ICRH $0014 Read: Write: Reset: ICRL $0015 Read: Write: Reset: = Unimplemented Unaffected by reset Bit 7 Bit 7 6 Bit 6 5 Bit 5 Unaffected by reset 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
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Bit 7 Bit 15
6 Bit 14
5 Bit 13
4 Bit 12
3 Bit 11
2 Bit 10
1 Bit 9
Bit 0 Bit 8
Figure 8-6. Input Capture Registers (ICRH and ICRL)
NOTE:
To prevent interrupts from occurring between readings of ICRH and ICRL, set the interrupt flag in the condition code register before reading ICRH, and clear the flag after reading ICRL.
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Capture/Compare Timer
8.4.6 Output Compare Registers When the value of the 16-bit counter matches the value in the output compare registers (OCRH and OCRL), the planned TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL is written. Reading or writing to OCRL after the timer status register clears the output compare flag (OCF).
OCRH $0016
Bit 7 Bit 15
6 Bit 14
5 Bit 13
4 Bit 12
3 Bit 11
2 Bit 10
1 Bit 9
Bit 0 Bit 8
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Write: Read: Reset: Unaffected by reset
OCRL $0017 Read:
Bit 7 Bit 7
6 Bit 6
5 Bit 5
4 Bit 4
3 Bit 3
2 Bit 2
1 Bit 1
Bit 0 Bit 0
Write: Reset: Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL) To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. Disable interrupts by setting the I bit in the condition code register. 2. Write to OCRH. Compares are now inhibited until OCRL is written. 3. Clear bit OCF by reading timer status register (TSR). 4. Enable the output compare function by writing to OCRL. 5. Enable interrupts by clearing the I bit in the condition code register.
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Capture/Compare Timer Timer During Wait Mode
8.5 Timer During Wait Mode
The CPU clock halts during the wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode.
8.6 Timer During Stop Mode
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In the stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt. If STOP is exited by reset, the counters are forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any timer flags or wake up the MCU, but if an interrupt is used to exit stop mode, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
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Capture/Compare Timer
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Section 9. Serial Communications Interface (SCI)
9.1 Content
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SCI Receiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SCI Transmitter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Receiver Wakeup Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Address Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Receive Data In (RDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Start Bit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Transmit Data Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
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9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13
9.14 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.14.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.14.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 9.14.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 9.14.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.14.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Serial Communications Interface (SCI) 9.2 Introduction
This section describes the on-chip asynchronous serial communications interface (SCI). The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator.
9.3 Features
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Features of the SCI include: * * * * * * Standard mark/space non-return-to-zero format Full-duplex operation 32 programmable baud rates Programmable 8-bit or 9-bit character length Separately enabled transmitter and receiver Two receiver wakeup methods: - Idle line wakeup - Address mark wakeup * Interrupt-driven operation capability with five interrupt flags: - Transmitter data register empty - Transmission complete - Transmission data register full - Receiver overrun - Idle receiver input * * Receiver framing error detection 1/16 bit-time noise detection
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Serial Communications Interface (SCI) Features
INTERNAL BUS SCI INTERRUPT + $0011 TRANSMIT DATA REGISTER $0011 RECEIVE DATA REGISTER
& TDO PIN TRANSMIT DATA SHIFT REGISTER
&
&
&
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+ SCSR $0010 1 FE
$000F SCCR2 TIE TCIE RIE ILIE TE RE SBK RWU
7 6 5 4 3 2 1 0
RECEIVE DATA SHIFT REGISTER
RDI PIN
7 TRDE
6 TC
5 RDRF
4 IDLE
3 OR
2 NF
WAKEUP UNIT
TE
SBK
7 FLAG CONTROL RECEIVER CONTROL RECEIVER CLOCK
TRANSMITTER CONTROL
7 R8
6 T8
5
4 M
3 WAKE
2
1
0
SCCR1 $000E
Figure 9-1. Serial Communications Interface Block Diagram
NOTE:
The serial communications data register (SCI SCDR) is controlled by the internal R/W signal. It is the transmit data register when written to and the receive data register when read.
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Serial Communications Interface (SCI) 9.4 SCI Receiver Features
Features of the SCI receiver include: * * * * * Receiver wakeup function (idle line or address bit) Idle line detection Framing error detection Noise detection Overrun detection Receiver data register full flag
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*
9.5 SCI Transmitter Features
Features of the SCI transmitter include: * * * Transmit data register empty flag Transmit complete flag Send break
9.6 Functional Description
A block diagram of the SCI is shown in Figure 9-1. Option bits in serial control register1 (SCCR1) select the wakeup method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides control bits that individually enable the transmitter and receiver, enable system interrupts, and provide the wakeup enable bit (RWU) and the send break code bit (SBK). Control bits in the baud rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and receiver. Data transmission is initiated by writing to the serial communications data register (SCDR). Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The transfer of data to the transmit data shift
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Serial Communications Interface (SCI) Functional Description
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register is synchronized with the bit rate clock (see Figure 9-2). All data is transmitted least significant bit first. Upon completion of data transmission, the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble, or break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If the transmitter is disabled, and the data, preamble, or break (in the transmit data shift register) has been sent, the TC bit will be set also. This will also generate an interrupt if the transmission complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the character being transmitted will be completed before the transmitter gives up control of the TDO pin. When SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR may be set if data reception errors occurred. An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects idle line transmission) in SCSR is set. This allows a receiver that is not in the wakeup mode to detect the end of a message, or the preamble of a new message, or to re-synchronize with the transmitter. A valid character must be received before the idle line condition or the IDLE bit will not be set and idle line interrupt will not be generated.
SCP0-SCP1 OSC FREQ (fOSC) /2 BUS FREQ (fOP) SCI PRESCALER SELECT CONTROL N
SCR0-SCR2 SCI RATE SELECT CONTROL M SCI RECEIVE CLOCK (RT) /16 SCI TRANS CLOCK (TX)
Figure 9-2. Rate Generator Division
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Serial Communications Interface (SCI) 9.7 Data Format
Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The non-return-tozero (NRZ) data format shown in Figure 9-3 is used and must meet the following criteria: * The idle line is brought to a logic 1 state prior to transmission/reception of a character. A start bit (logic 0) is used to indicate the start of a frame. The data is transmitted and received least significant bit first. A stop bit (logic 1) is used to indicate the end of a frame. A frame consists of a start bit, a character of eight or nine data bits, and a stop bit. A break is defined as the transmission or reception of a low (logic 0) for at least one complete frame time.
CONTROL BIT M SELECTS 8- OR 9-BIT DATA IDLE LINE 0 START 1 2 3 4 5 6 7 8 0 STOP START
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* * *
*
Figure 9-3. Data Format
9.8 Receiver Wakeup Operation
The receiver logic hardware also supports a receiver wakeup function which is intended for systems having more than one receiver. With this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. The wakeup function allows receivers not addressed to remain in a dormant state for the remainder of the unwanted message. This eliminates any further software overhead to service the remaining characters of the unwanted message and thus improves system performance.
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Serial Communications Interface (SCI) Idle Line Wakeup
The receiver is placed in wakeup mode by setting the receiver wakeup bit (RWU) in the SCCR2 register. While RWU is set, all of the receiverrelated status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set).
NOTE:
The idle line detect function is inhibited while the RWU bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do so. Normally, RWU is set by software and is cleared automatically in hardware by one of these methods: idle line wakeup or address mark wakeup.
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9.9 Idle Line Wakeup
In idle line wakeup mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle is defined as a continuous logic high level on the RDI line for 10 (or 11) full bit times. Systems using this type of wakeup must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message.
9.10 Address Mark Wakeup
In address mark wakeup, the most significant bit (MSB) in a character is used to indicate whether it is an address (logic 1) or data (logic 0) character. Sleeping receivers will wake up whenever an address character is received. Systems using this method for wakeup would set the MSB of the first character of each message and leave it clear for all other characters in the message. Idle periods may be present within messages and no idle time is required between messages for this wakeup method.
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Serial Communications Interface (SCI) 9.11 Receive Data In (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus. The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred to as the RT rate in Figure 9-4 and as the receiver clock in Figure 9-6. The receiver clock generator is controlled by the baud rate register; however, the SCI is synchronized by the start bit, independent of the transmitter.
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Once a valid start bit is detected, the start bit, each data bit, and the stop bit are sampled three times at RT intervals 8 RT, 9 RT, and 10 RT (1 RT is the position where the bit is expected to start), as shown in Figure 9-5. The value of the bit is determined by voting logic which takes the value of the majority of the samples. A noise flag is set when all three samples on a valid start bit or data bit or the stop bit do not agree.
16X INTERNAL SAMPLING CLOCK
RT CLOCK EDGES FOR ALL THREE EXAMPLES IDLE RDI 1 1 1 1 1 1 1 1
1RT START
2RT
3RT
4RT
5RT
6RT
7RT
0 START
0
0
0
NOISE
RDI 1 1 1 1 1 1 1 1 0 0 1 0
NOISE RDI 1 1 1 0 1 1 1 1
START
0
0
0
0
Figure 9-4. SCI Examples of Start Bit Sampling Techniques
PREVIOUS BIT RDI 16RT 1RT 8RT 9RT 10RT 16RT 1RT SAMPLES NEXT BIT
Figure 9-5. SCI Sampling Technique Used on All Bits
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Serial Communications Interface (SCI) Start Bit Detection
9.12 Start Bit Detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as the start edge verification samples in Figure 9-4). If at least two of these three verification samples detect a logic 0, a valid start bit has been detected; otherwise, the line is assumed to be idle. A noise flag is set if all three verification samples do not detect a logic 0. Thus, a valid start bit could be assumed with a set noise flag present.
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If a framing error has occurred without detection of a break (10 0s for 8-bit format or 11 0s for 9-bit format), the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed artificially. The last bit received in the data shift register is inverted to a logic 1, and the three logic 1 start qualifiers (shown in Figure 9-4) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see Figure 9-6); therefore, the start bit will be accepted no sooner than it is anticipated. If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $003B) produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic 1 before the start bit can be recognized (see Figure 9-7).
DATA RDI
EXPECTED STOP
ARTIFICIAL EDGE START BIT
DATA
DATA SAMPLES a) Case 1: Receive line low during artificial edge DATA RDI EXPECTED STOP DATA START BIT
START EDGE
DATA SAMPLES b) Case 2: Receive line high during expected start edge
Figure 9-6. SCI Artificial Start Following a Frame Error
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Serial Communications Interface (SCI)
EXPECTED STOP BREAK RDI
DETECTED AS VALID START EDGE START BIT START START EDGE QUALIFIERS VERIFICATION SAMPLES
DATA SAMPLES
Figure 9-7. SCI Start Bit Following a Break
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9.13 Transmit Data Out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the output line. Data format is as discussed in 9.7 Data Format and shown in Figure 9-3. The transmitter generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock.
9.14 SCI I/O Registers
The following I/O registers control and monitor SCI operation: * * * * SCI data register (SCDR) SCI control register 1 (SCCR1) SCI control register 2 (SCCR2) SCI status register (SCSR)
9.14.1 SCI Data Register The SCI data register (SCDR), shown in Figure 9-8, is the buffer for characters received and for characters transmitted.
$0011 Read: Write: Reset: Unaffected by reset Bit 7 BIT7 6 BIT6 5 BIT55 4 BIT4 3 BIT3 2 BIT2 1 BIT1 Bit 0 BIT0
Figure 9-8. SCI Data Register (SCDR)
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Serial Communications Interface (SCI) SCI I/O Registers
9.14.2 SCI Control Register 1 The SCI control register 1 (SCCR1), shown in Figure 9-9, has these functions: * * * Stores ninth SCI data bit received and ninth SCI data bit transmitted Controls SCI character length Controls SCI wakeup method
Bit 7 R8 Write: Reset: U U 0 U U 0 0 0 6 T8 5 4 M 3 WAKE 2 1 Bit 0
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$000E Read:
= Unimplemented
U = Undetermined
Figure 9-9. SCI Control Register 1 (SCCR1) R8 -- Bit 8 (Received) When the SCI is receiving 9-bit characters, R8 is the ninth bit of the received character. R8 receives the ninth bit at the same time that the SCDR receives the other eight bits. Resets have no effect on the R8 bit. T8 -- Bit 8 (Transmitted) When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit register. Resets have no effect on the T8 bit. M -- Character Length Bit This read/write bit determines whether SCI characters are 8 bits long or 9 bits long. The ninth bit can be used as an extra stop bit, as a receiver wakeup signal, or as a mark or space parity bit. Resets have no effect on the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters
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Serial Communications Interface (SCI)
WAKE -- Wakeup Method Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit (MSB) position of a received character or an idle condition on the PD0/RDI pin. Resets have no effect on the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup
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9.14.3 SCI Control Register 2 SCI control register 2 (SCCR2), shown in Figure 9-10, has these functions: * * * * * *
$000F Read: TIE Write: Reset: 0 0 0 0 0 0 0 0 TCIE RIE ILIE TE RE RWU SBK
Enables the SCI receiver and SCI receiver interrupts Enables the SCI transmitter and SCI transmitter interrupts Enables SCI receiver idle interrupts Enables SCI transmission complete interrupts Enables SCI wakeup Transmits SCI break characters
Bit 7 6 5 4 3 2 1 Bit 0
Figure 9-10. SCI Control Register 2 (SCCR2) TIE -- Transmit Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TDRE flag becomes set. Resets clear the TIE bit. 1 = TDRE interrupt requests enabled 0 = TDRE interrupt requests disabled
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Serial Communications Interface (SCI) SCI I/O Registers
TCIE -- Transmission Complete Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TC flag becomes set. Resets clear the TCIE bit. 1 = TC interrupt requests enabled 0 = TC interrupt requests disabled RIE -- Receiver Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the RDRF flag or the OR flag becomes set. Resets clear the RIE bit. 1 = RDRF interrupt requests enabled 0 = RDRF interrupt requests disabled ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the IDLE bit becomes set. Resets clear the ILIE bit. 1 = IDLE interrupt requests enabled 0 = IDLE interrupt requests disabled TE -- Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the PD1/TDO pin. Resets clear the TE bit. 1 = Transmission enabled 0 = Transmission disabled RE -- Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. Resets clear the RE bit. 1 = Receiver enabled 0 = Receiver disabled
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Serial Communications Interface (SCI)
RWU -- Receiver Wakeup Enable Bit This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears the RWU bit and returns the receiver to normal operation. The WAKE bit in SCCR1 determines whether an idle input or an address mark brings the receiver out of standby state. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation
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SBK -- Send Break Bit Setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops the break codes and transmits a logic 1 as a start bit. Reset clears the SBK bit. 1 = Break codes being transmitted 0 = No break codes being transmitted
9.14.4 SCI Status Register The SCI status register (SCSR), shown in Figure 9-11, contains flags to signal the following conditions: * * * * * * Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data SCDR complete Receiver input idle Noisy data Framing error
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Serial Communications Interface (SCI) SCI I/O Registers
$0010 Read:
Bit 7 TDRE
6 TC 1
5 RDRF 0
4 IDLE 0
3 OR 0
2 NF 0
1 FE 0
Bit 0
Write: Reset: 1 --
= Unimplemented
Figure 9-11. SCI Status Register (SCSR) TDRE -- Transmit Data Register Empty Flag
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This clearable, read-only flag is set when the data in the SCDR transfers to the transmit shift register. TDRE generates an interrupt request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by reading the SCSR with TDRE set and then writing to the SCDR. Reset sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to avoid an instant interrupt request when turning the transmitter on. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC -- Transmission Complete Flag This clearable, read-only flag is set when the TDRE bit is set, and no data, preamble, or break character is being transmitted. TDRE generates an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC bit by reading the SCSR with TC set, and then writing to the SCDR. Reset sets the TC bit. Software must initialize the TC bit to logic 0 to avoid an instant interrupt request when turning the transmitter on. 1 = No transmission in progress 0 = Transmission in progress RDRF -- Receive Data Register Full Flag This clearable, read-only flag is set when the data in the receive shift register transfers to the SCI data register. RDRF generates an interrupt request if the RIE bit in the SCCR2 is also set. Clear the RDRF bit by reading the SCSR with RDRF set and then reading the SCDR. 1 = Received data available in SCDR 0 = Received data not available in SCDR
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Serial Communications Interface (SCI)
IDLE -- Receiver Idle Flag This clearable, read-only flag is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an interrupt request if the ILIE bit in the SCCR2 is also set. Clear the ILIE bit by reading the SCSR with IDLE set and then reading the SCDR. 1 = Receiver input idle 0 = Receiver input not idle OR -- Receiver Overrun Flag
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This clearable, read-only flag is set if the SCDR is not read before the receive shift register receives the next word. OR generates an interrupt request if the RIE bit in the SCCR2 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading the SCSR with OR set and then reading the SCDR. 1 = Receive shift register full and RDRF = 1 0 = No receiver overrun NF -- Receiver Noise Flag This clearable, read-only flag is set when noise is detected in data received in the SCI data register. Clear the NF bit by reading the SCSR and then reading the SCDR. 1 = Noise detected in SCDR 0 = No noise detected in SCDR FE -- Receiver Framing Error Flag This clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character shifted into the receive shift register. If the received word causes both a framing error and an overrun error, the OR flag is set and the FE flag is not set. Clear the FE bit by reading the SCSR and then reading the SCDR. 1 = Framing error 0 = No framing error
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Serial Communications Interface (SCI) SCI I/O Registers
9.14.5 Baud Rate Register The baud rate register (BAUD), shown in Figure 9-12, selects the baud rate for both the receiver and the transmitter.
$000D Read: SCP1 Write: Reset: -- -- 0 0 -- U U U SCP0 SCR2 SCR1 SCR0 Bit 7 6 5 4 3 2 1 Bit 0
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= Unimplemented
U = Undetermined
Figure 9-12. Baud Rate Register (BAUD) SCP1 -- SCP0-SCI Prescaler Select Bits These read/write bits control prescaling of the baud rate generator clock, as shown in Table 9-1. Reset clears both SCP1 and SCP0. Table 9-1. Baud Rate Generator Clock Prescaling
SCP[1:0] 00 01 10 11 Baud Rate Generator Clock Internal Clock / 1 Internal Clock / 3 Internal Clock / 4 Internal Clock / 13
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Serial Communications Interface (SCI)
SCR2 -- SCR0-SCI Baud Rate Select Bits These read/write bits select the SCI baud rate, as shown in Table 9-2. Resets have no effect on the SCR2-SCR0 bits. Table 9-2. Baud Rate Selection
SCR[2:0] 000 001 SCI Baud Rate (Baud) Prescaled Clock / 1 Prescaled Clock / 2 Prescaled Clock / 4 Prescaled Clock / 8 Prescaled Clock / 16 Prescaled Clock / 32 Prescaled Clock / 64 Prescaled Clock / 128
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010 011 100 101 110 111
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Section 10. Serial Peripheral Interface (SPI)
10.1 Content
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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10.3
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.4.1 Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . 105 10.4.2 Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . 105 10.4.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.4.4 Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 10.6.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . 109 10.6.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . 111 10.6.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . .113
10.2 Introduction
The serial peripheral interface (SPI) is an interface built into the device which allows several MC68HC05 MCUs, or MC68HC05 MCU plus peripheral devices, to be interconnected within a single printed circuit board. In an SPI, separate wires are required for data and clock. In the SPI format, the clock is not included in the data stream and must be furnished as a separate signal. An SPI system may be configured in one containing one master MCU and several slave MCUs, or in a system in which an MCU is capable of being a master or a slave.
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Serial Peripheral Interface (SPI) 10.3 Features
Features include: * * * * Full-duplex, four-wire synchronous transfers Master or slave operation Bus frequency divided by 2 (maximum) master bit frequency Bus frequency (maximum) slave bit frequency Four programmable master bit rates Programmable clock polarity and phase End of transmission interrupt flag Write collision flag protection Master-master mode fault protection capability
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* * * * *
10.4 SPI Signal Description
The four basic signals (MOSI, MISO, SCK, and SS) are described in the following paragraphs. Each signal function is described for both the master and slave modes.
NOTE:
In C9A mode, any SPI output line has to have its corresponding data direction register bit set. If this bit is clear, the line is disconnected from the SPI logic and becomes a general-purpose input line. When the SPI is enabled, any SPI input line is forced to act as an input regardless of what is in the corresponding data direction register bit.
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Serial Peripheral Interface (SPI) SPI Signal Description
SS
SCK
CPOL = 0 CPHA = 0
SCK
CPOL = 0 CPHA = 1
SCK
CPOL = 1 CPHA = 0
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SCK
CPOL = 1 CPHA = 1
MISO/MOSI MSB 6 5 4 3 2 1 0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
10.4.1 Master In Slave Out (MISO) The MISO line is configured as an input in a master device and as an output in a slave device. It is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. The MISO line of a slave device is placed in the high-impedance state if the slave is not selected.
10.4.2 Master Out Slave In (MOSI) The MOSI line is configured as an output in a master device and as an input in a slave device. It is one of the two lines that transfer serial data in one direction with the most significant bit sent first.
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Serial Peripheral Interface (SPI)
10.4.3 Serial Clock (SCK) The master clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input on a slave device. As shown in Figure 10-1, four possible timing relationships may be chosen by using control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate with the same timing. The master device always places data on the MOSI line a half cycle before the clock edge (SCK), in order for the slave device to latch the data. Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device, SPR0 and SPR1 have no effect on the operation of the SPI.
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10.4.4 Slave Select (SS) The slave select (SS) input line is used to select a slave device. It has to be low prior to data transactions and must stay low for the duration of the transaction.The SS line on the master must be tied high. In master mode, if the SS pin is pulled low during a transmission, a mode fault error flag (MODF) is set in the SPSR. In master mode the SS pin can be selected to be a general-purpose output (when configured as an MC68HC05C9A) by writing a 1 in bit 5 of the port D data direction register, thus disabling the mode fault circuit. When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as CPHA = 1 clock modes are used.
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Serial Peripheral Interface (SPI) Functional Description
10.5 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device transmits data to a slave via the MOSI line, the slave device responds by sending data to the master device via the master's MISO line. This implies full duplex transmission with both data out and data in synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is used to signify that the I/O operation has been completed.
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S M SPI SHIFT REGISTER 76543210 M S PD2/ MISO PD3/ MOSI
INTERNAL DATA BUS
SPDR ($000C)
INTERNAL CLOCK (XTAL /2)
SPIE SPE MSTR SPI CONTROL
SPIF WCOL MODF
/2
DIVIDER / 4 / 16
SHIFT CLOCK SPI INTERRUPT REQUEST PD5/ SS SPI CLOCK (SLAVE) SPI CLOCK (MASTER)
/ 32
SELECT
SPI CLOCK (MASTER)
CLOCK LOGIC
PD4/ SCK
SPR1
SPR0 7 SPI CONTROL REGISTER (SPCR) SPIE SPI STATUS REGISTER (SPSR) SPIF SPI DATA REGISTER (SPDR) BIT 7
MSTR 6 SPE WCOL BIT 6
CPHA 5 DWOM 0 BIT 5
CPOL 4 MSTR MODF BIT 4
3 CPOL 0 BIT 3
2 CPHA 0 BIT 2
1 SPR1 0 BIT 1
0 SPR2 0 BIT 0
$000A $000B $000C
Figure 10-2. Serial Peripheral Interface Block Diagram
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Serial Peripheral Interface (SPI)
The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR is set. In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR, until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of data and then SCK goes idle again.
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In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin. Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave's MISO line. Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
PD3/MOSI SPI SHIFT REGISTER 76543210 PD2/MISO PD5/SS I/O PORT SPDR ($000C) PD4/SCK MASTER MCU SLAVE MCU SPDR ($000C) SPI SHIFT REGISTER 76543210
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
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Serial Peripheral Interface (SPI) SPI Registers
10.6 SPI Registers
Three registers in the SPI provide control, status, and data storage functions. These registers are called the serial peripheral control register (SPCR), serial peripheral status register (SPSR), and serial peripheral data I/O register (SPDR) and are described in the following paragraphs.
10.6.1 Serial Peripheral Control Register
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The SPI control register (SPCR), shown in Figure 10-4, controls these functions: * * * * * *
$000A Read: SPIE Write: Reset: 0 0 SPE
Enables SPI interrupts Enables the SPI system Selects between standard CMOS or open drain outputs for port D (C9A mode only) Selects between master mode and slave mode Controls the clock/data relationship between master and slave Determines the idle level of the clock pin
Bit 7 6 5 DWOM (C9A) 0 4 MSTR 0 3 CPOL 0 2 CPHA 1 1 SPR1 U Bit 0 SPR0 U
U = Undetermined
Figure 10-4. SPI Control Register (SPCR) SPIE -- Serial Peripheral Interrupt Enable Bit This read/write bit enables SPI interrupts. Reset clears the SPIE bit. 1 = SPI interrupts enabled 0 = SPI interrupts disabled
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Serial Peripheral Interface (SPI)
SPE -- Serial Peripheral System Enable Bit This read/write bit enables the SPI. Reset clears the SPE bit. 1 = SPI system enabled 0 = SPI system disabled DWOM -- Port D Wire-OR Mode Option Bit This read/write bit disables the high side driver transistors on port D outputs so that port D outputs become open-drain drivers. DWOM affects all seven port D pins together. This option is only available when configured as a C9A. 1 = Port D outputs act as open-drain outputs. 0 = Port D outputs are normal CMOS outputs. MSTR -- Master Mode Select Bit This read/write bit selects master mode operation or slave mode operation. Reset clears the MSTR bit. 1 = Master mode 0 = Slave mode CPOL -- Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high. This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data relationship between master and slave. See Figure 10-1. CPHA -- Clock Phase Bit The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA = 0, the shift clock is the OR of SCK with SS. As soon as SS goes low, the transaction begins and the first edge on SCK invokes the first data sample. When CPHA=1, the SS pin may be thought of as a simple output enable control. See Figure 10-1.
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Serial Peripheral Interface (SPI) SPI Registers
SPR1 and SPR0 -- SPI Clock Rate Selects These read/write bits select one of four master mode serial clock rates, as shown in Table 10-1. They have no effect in the slave mode. Table 10-1. SPI Clock Rate Selection
SPR[1:0] 00 SPI Clock Rate Internal Clock / 2 Internal Clock / 4 Internal Clock / 16 Internal Clock / 32
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01 10 11
10.6.2 Serial Peripheral Status Register The SPI status register (SPSR), shown in Figure 10-5, contains flags to signal the following conditions: * * *
$000B Read: Write: Reset: 0 0 0 0 0 0 0 0
SPI transmission complete Write collision Mode fault
Bit 7 SPIF 6 WCOL 5 4 MODF 3 2 1 Bit 0
= Unimplemented
Figure 10-5. SPI Status Register SPIF -- SPI Transfer Complete Flag The serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. Clearing the SPIF bit is accomplished by reading the SPSR (with
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SPIF set) followed by an access of the SPDR. Following the initial transfer, unless SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited. WCOL -- Write Collision Bit The write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. If CPHA is 0, a transfer is said to begin when SS goes low and the transfer ends when SS goes high after eight clock cycles on SCK. When CPHA is 1, a transfer is said to begin the first time SCK becomes active while SS is low and the transfer ends when the SPIF flag gets set. Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access to SPDR. MODF -- Mode Fault The mode fault flag indicates that there may have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state. The MODF bit is normally clear, and is set only when the master device has its SS pin pulled low. Setting the MODF bit affects the internal serial peripheral interface system in the following ways. 1. An SPI interrupt is generated if SPIE = 1. 2. The SPE bit is cleared. This disables the SPI. 3. The MSTR bit is cleared, thus forcing the device into the slave mode. Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to the SPCR. Control bits SPE and MSTR may be restored by user software to their original state during this clearing sequence or after the MODF bit has been cleared. When configured as an MC68HC05C9A, it is also necessary to restore DDRD after a mode fault. Bits 5 and 3-0 -- Not Implemented These bits always read 0.
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Serial Peripheral Interface (SPI) SPI Registers
10.6.3 Serial Peripheral Data I/O Register The serial peripheral data I/O register (SPDR), shown in Figure 10-6, is used to transmit and receive data on the serial bus. Only a write to this register will initiate transmission/reception of another byte and this will only occur in the master device. At the completion of transmitting a byte of data, the SPIF status bit is set in both the master and slave devices. When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF must be cleared by the time a second transfer of the data from the shift register to the read buffer is initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into the shift register for transmission.
$000C Read: SPD7 Write: Reset: Unaffected by reset SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 Bit 7 6 5 4 3 2 1 Bit 0
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Figure 10-6. PI Data Register (SPDR)
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Section 11. Instruction Set
11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .119 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . 120 11.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .123 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 11.5 11.6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is
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Instruction Set
stored in the index register, and the low-order product is stored in the accumulator.
11.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are:
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* * * * * * * *
Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative
11.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
11.3.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
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Instruction Set Addressing Modes
11.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
11.3.4 Extended
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Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
11.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.
11.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE.
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Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
11.3.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.
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11.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
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11.4 Instruction Types
The MCU instructions fall into the following five categories: * * * * * Register/memory instructions Read-modify-write instructions Jump/branch instructions Bit manipulation instructions Control instructions
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11.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1. Register/Memory Instructions
Instruction Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
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11.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.
NOTE:
Do not use read modify-write operations on write-only registers. Table 11-2. Read-Modify-Write Instructions
Instruction Mnemonic ASL ASR BCLR (1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2)
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Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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Instruction Set Instruction Types
11.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register.
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Table 11-3. Jump and Branch Instructions
Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR
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Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine
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11.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 11-4. Bit Manipulation Instructions
Instruction Mnemonic BCLR BRCLR BRSET BSET
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Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set
11.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 11-5. Control Instructions
Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA
WAIT
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Instruction Set 11.5 Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 1 of 6)
Opcode Source Form
ADC ADC ADC ADC ADC ADC ADD ADD ADD ADD ADD ADD #opr opr opr opr,X opr,X ,X #opr opr opr opr,X opr,X ,X
Operation
Description
H I NZC
Add with Carry
A (A) + (M) + (C)
--
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IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
ii A9 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 ii A4 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3
Add without Carry
A (A) + (M)
--
AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Logical AND
A (A) (M)
----
--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----
ff dd
Arithmetic Shift Right
b7 b0
C
----
ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- ---------- ---------- REL REL REL REL REL REL
BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C Z = 0 PC (PC) + 2 + rel ? C = 0
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Effect on CCR
Operand
Address Mode
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Instruction Set Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 2 of 6)
Opcode Source Form
BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
H I NZC
---------- ----------
REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
2F 2E
rr rr
Bit Test Accumulator with Memory Byte
(A) (M)
----
--
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ii A5 2 B5 dd 3 C5 hh ll 4 D5 ee ff 5 E5 ff 4 F5 3 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? C Z = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1
---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if Bit n Clear
PC (PC) + 2 + rel ? Mn = 0
--------
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
----------
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
--------
BSET n opr
Set Bit n
Mn 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0
----------
REL
AD
rr
CLC CLI
Clear Carry Bit Clear Interrupt Mask
-------- 0 -- 0 ------
INH INH
98 9A
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Cycles
3 3 6 2 2
Effect on CCR
Operand
Address Mode
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Instruction Set
Table 11-6. Instruction Set Summary (Sheet 3 of 6)
Opcode Source Form
CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX CPX CPX CPX CPX CPX #opr opr opr opr,X opr,X ,X
Operation
Description
M $00 A $00 X $00 M $00 M $00
H I NZC
Clear Byte
---- 0 1 --
DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX
3F 4F 5F 6F 7F
dd
ff
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Compare Accumulator with Memory Byte
(A) - (M)
----
ii A1 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5
M (M) = $FF - (M) A (A) = $FF - (A) Complement Byte (One's Complement) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M) ----
1
ff
Compare Index Register with Memory Byte
(X) - (M)
----
ii A3 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5
DEC opr DECA DECX DEC opr,X DEC ,X EOR EOR EOR EOR EOR EOR #opr opr opr opr,X opr,X ,X
Decrement Byte
M A X M M
(M) - 1 (A) - 1 (X) - 1 (M) - 1 (M) - 1
----
--
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
----
--
ii A8 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5
INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
----
--
ff
Unconditional Jump
PC Jump Address
----------
BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2
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Cycles
5 3 3 6 5
Effect on CCR
Operand
Address Mode
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Instruction Set Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 4 of 6)
Opcode Source Form
JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA ORA ORA ORA ORA ORA #opr opr opr opr,X opr,X ,X
Operation
Description
H I NZC
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address
Jump to Subroutine
----------
DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX
BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 ii A6 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2
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Load Accumulator with Memory Byte
A (M)
----
--
Load Index Register with Memory Byte
X (M)
----
--
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff dd
Logical Shift Right
0 b7 b0
C
---- 0
ff
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
Negate Byte (Two's Complement)
----
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
----
--
AA ii 2 BA dd 3 CA hh ll 4 DA ee ff 5 EA ff 4 FA 3 39 49 59 69 79 dd 5 3 3 6 5
ROL opr ROLA ROLX ROL opr,X ROL ,X
Rotate Byte Left through Carry Bit
C b7 b0
----
ff
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Advance Information 127
Cycles
Effect on CCR
Operand
Address Mode
Freescale Semiconductor, Inc.
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 5 of 6)
Opcode Source Form
ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
H I NZC
Rotate Byte Right through Carry Bit
b7 b0
C
----
DIR INH INH IX1 IX INH
36 46 56 66 76 9C
dd
ff
Reset Stack Pointer
SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL)
----------
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RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB SUB SUB SUB SUB SUB #opr opr opr opr,X opr,X ,X
Return from Subroutine
----------
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
81
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
ii A2 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B 2 2
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
Store Accumulator in Memory
M (A)
----
--
B7 dd 4 C7 hh ll 5 D7 ee ff 6 E7 ff 5 F7 4 8E 2
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
----
--
BF dd 4 CF hh ll 5 DF ee ff 6 EF ff 5 FF 4 ii A0 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3
Subtract Memory Byte from Accumulator
A (A) - (M)
----
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte
INH
83
10
Advance Information 128 Instruction Set For More Information On This Product, Go to: www.freescale.com
MC68HC705C9A -- Rev. 4.0 MOTOROLA
Cycles
5 3 3 6 5 2 9 6
Effect on CCR
Operand
Address Mode
Freescale Semiconductor, Inc.
Instruction Set Opcode Map
Table 11-6. Instruction Set Summary (Sheet 6 of 6)
Opcode Source Form
TAX TST opr TSTA TSTX TST opr,X TST ,X TXA
Operation
Transfer Accumulator to Index Register
Description
X (A)
H I NZC
----------
INH DIR INH INH IX1 IX INH INH
97 3D 4D 5D 6D 7D 9F 8F dd
Test Memory Byte for Negative or Zero
(M) - $00
----
--
ff
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
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A (X)
---------- -- 0 ------
WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
opr PC PCH PCL REL rel rr SP X Z # () -( ) ? :
--
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
11.6 Opcode Map
See Table 11-7.
MC68HC705C9A -- Rev. 4.0 MOTOROLA Instruction Set For More Information On This Product, Go to: www.freescale.com
Advance Information 129
Cycles
2 4 3 3 5 4 2 2
Effect on CCR
Operand
Address Mode
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Table 11-7. Opcode Map
Read-Modify-Write DIR 3
3 NEGX 1 INH 2 2 2 1 2 2 2 2 2 1 1 1 1 1 1 1 1 2 5 6 CLR CLR IX IX1 1 3 CLRX INH 2 2 2 2 2 2 2 2 2 2 2 1 1 2 1 2 3 3 3 3 3 3 3 3 3 3 2 MSB LSB LSB of Opcode in Hexadecimal 3 2 3 3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 2 1 10 SWI INH 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 2 2 3 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 3 2 1 5 NEG 2 DIR 3 NEGA 1 INH 5 6 NEG NEG IX 2 IX1 1
Instruction Set
130
Control IX 7 8 9 A B C D E F
MSB LSB
Bit Manipulation Branch REL 2 4 5 6 INH INH IX1 INH INH IMM DIR EXT IX2 IX1 IX
Register/Memory
DIR
DIR
MSB LSB
0
1
Advance Information
0 1 2 3 4 5 6 7 8 9 A B C D E F
9 RTI 1 INH 6 RTS 1 INH 1 11 MUL INH 3 5 COMA COM INH 2 DIR 1 3 5 LSRA LSR INH 2 DIR 1 3 COMX INH 3 LSRX 1 INH 5 6 COM COM IX IX1 1 5 6 LSR LSR IX 2 IX1 1 2 SUB IMM 2 CMP IMM 2 SBC IMM 2 CPX IMM 2 AND IMM 2 BIT IMM 2 LDA IMM 5 ROR DIR 5 ASR 2 DIR 5 ASL/LSL 2 DIR 5 ROL 2 DIR 5 DEC 2 DIR 2 EOR IMM 2 ADC IMM 2 ORA IMM 2 ADD IMM 3 RORA INH 3 ASRA 1 INH 3 ASLA/LSLA 1 INH 3 ROLA 1 INH 3 DECA 1 INH 3 RORX INH 3 ASRX 1 INH 3 ASLX/LSLX 1 INH 3 ROLX 1 INH 3 DECX 1 INH 6 ROR IX1 6 ASR 2 IX1 6 ASL/LSL 2 IX1 6 ROL 2 IX1 6 DEC 2 IX1 5 ROR IX 5 ASR 1 IX 5 ASL/LSL 1 IX 5 ROL 1 IX 5 DEC 1 IX 5 INC 2 DIR 4 TST 2 DIR 3 INCA 1 INH 3 TSTA 1 INH 3 INCX 1 INH 3 TSTX 1 INH 5 6 INC INC IX 2 IX1 1 4 5 TST TST IX 2 IX1 1 2 TAX INH 2 CLC INH 2 SEC INH 2 CLI INH 2 SEI INH 2 RSP INH 2 NOP INH 6 BSR 2 REL 2 2 LDX 2 IMM 2 2 STOP INH 2 2 TXA WAIT INH 1 INH 1 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS/BLO 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL 2 5 CLR DIR 1 1 3 CLRA INH 3 SUB DIR 3 CMP DIR 3 SBC DIR 3 CPX DIR 3 AND DIR 3 BIT DIR 3 LDA DIR 4 STA DIR 3 EOR DIR 3 ADC DIR 3 ORA DIR 3 ADD DIR 2 JMP DIR 5 JSR DIR 3 LDX DIR 4 STX DIR 4 SUB EXT 4 CMP EXT 4 SBC EXT 4 CPX EXT 4 AND EXT 4 BIT EXT 4 LDA EXT 5 STA EXT 4 EOR EXT 4 ADC EXT 4 ORA EXT 4 ADD EXT 3 JMP EXT 6 JSR EXT 4 LDX EXT 5 STX EXT 5 SUB IX2 5 CMP IX2 5 SBC IX2 5 CPX IX2 5 AND IX2 5 BIT IX2 5 LDA IX2 6 STA IX2 5 EOR IX2 5 ADC IX2 5 ORA IX2 5 ADD IX2 4 JMP IX2 7 JSR IX2 5 LDX IX2 6 STX IX2 4 SUB IX1 4 CMP IX1 4 SBC IX1 4 CPX IX1 4 AND IX1 4 BIT IX1 4 LDA IX1 5 STA IX1 4 EOR IX1 4 ADC IX1 4 ORA IX1 4 ADD IX1 3 JMP IX1 6 JSR IX1 4 LDX IX1 5 STX IX1 3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX
0
1
2
3
4
5
6
7
8
9
A
B
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Instruction Set For More Information On This Product, Go to: www.freescale.com
0 0
REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
C
D
E
F
5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR MSB of Opcode in Hexadecimal Number of Cycles 5 BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode
5 BSET0 2 DIR 5 BCLR0 2 DIR 5 BSET1 2 DIR 5 BCLR1 2 DIR 5 BSET2 2 DIR 5 BCLR2 2 DIR 5 BSET3 2 DIR 5 BCLR3 2 DIR 5 BSET4 2 DIR 5 BCLR4 2 DIR 5 BSET5 2 DIR 5 BCLR5 2 DIR 5 BSET6 2 DIR 5 BCLR6 2 DIR 5 BSET7 2 DIR 5 BCLR7 2 DIR
MC68HC705C9A -- Rev. 4.0
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
MOTOROLA
Freescale Semiconductor, Inc.
Advance Information -- MC68HC705C9A
Section 12. Electrical Specifications
12.1 Contents
12.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.0-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 135 3.3-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 136 5.0-Vdc Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.3-Vdc Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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12.3 12.4 12.5 12.6 12.7 12.8 12.9
12.10 5.0-Vdc Serial Peripheral Interface Timing . . . . . . . . . . . . . . . 142 12.11 3.3- Vdc Serial Peirpheral Interface Timing . . . . . . . . . . . . . . 143
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Advance Information 131
Freescale Semiconductor, Inc.
Electrical Specifications 12.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIn and VOut within the range VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
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Rating Supply voltage Input voltage Normal operation Bootloader mode (IRQ pin only) Current drain per pin (Excluding VDD and VSS) Storage temperature range
Symbol VDD VIn
Value -0.3 to +7.0 VSS -0.3 to VDD + 0.3 VSS -0.3 to 2 x VDD + 0.3 25 -65 to +150
Unit V
V
I TSTG
mA C
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 12.6 5.0-Vdc Electrical Characteristics for guaranteed operating conditions.
12.3 Operating Temperature
Characteristic Operating temperature range Symbol TA Value -40 to +85 Unit C
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MC68HC705C9A -- Rev. 4.0 MOTOROLA
Freescale Semiconductor, Inc.
Electrical Specifications Thermal Characteristics
12.4 Thermal Characteristics
Characteristic Thermal resistance plastic dual in-line (PDIP) Thermal resistance plastic leaded chip carrier (PLCC) Thermal resistance quad flat pack (QFP) Thermal resistance plastic shrink DIP (SDIP) Symbol JA JA JA JA Value 60 70 95 60 Unit C/W C/W C/W C/W
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12.5 Power Considerations
The average chip-junction temperature, TJ, in C, can be obtained from: TJ = TA + (PD x JA) where: TA = Ambient temperature, C JA = Package thermal resistance, junction to ambient, C/W PD = PINT + PI/O PINT = IDD x VDD watts (chip internal power) PI/O = Power dissipation on input and output pins (user determined) For most applications PI/O PINT and can be neglected. The following is an approximate relationship between PD and TJ (neglecting PJ): PD = K / (TJ + 273 C) Solving equations (1) and (2) for K gives: K = PD x (TA + 273 C) + JA x (PD)2 (3) (2) (1)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
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Electrical Specifications
VDD R2 SEE TABLE TEST POINT C (SEE TABLE) R1 (SEE TABLE)
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VDD = 4.5 V
Pins PA7-PA0 PB7-PB0 PC7-PC0 PD5-PD0, PD7 R1 R2 C
3.26
2.38
50 pF
VDD = 3.0 V
Pins PA7-PA0 PB7-PB0 PC7-PC0 PD5-PD0, PD7 R1 R2 C
10.91
6.32
50 pF
Figure 12-1. Test Load
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MC68HC705C9A -- Rev. 4.0 MOTOROLA
Freescale Semiconductor, Inc.
Electrical Specifications 5.0-Vdc Electrical Characteristics
12.6 5.0-Vdc Electrical Characteristics
Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (ILoad = -0.8 mA) PA7-PA0, PB7-PB0, PC6-PC0, TCMP, PD7, PD0 (ILoad = -1.6 mA) PD5-PD1 (ILoad = -5.0 mA) PC7 Symbol VOL VOH Min -- VDD -0.1 Typ(2) -- -- Max 0.1 -- Unit V
VOH
VDD -0.8 VDD -0.8 VDD -0.8
-- -- --
-- -- --
V
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Output low voltage (ILoad = 1.6 mA) PA7-PA0, PB7-PB0, PC6-PC0, PD7, PD5-PD0, TCMP (ILoad = 10 mA) PC7 Input high voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Input low voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Supply current (4.5-5.5 Vdc @ fOP = 2.1 MHz) Run(3) Wait Stop(5) 25C -40 to 85 C I/O ports hi-Z leakage current PA7-PA0, PB7-PB0 (without pullup) PC7-PC0, PD7, PD5-PD0 Input current RESET, IRQ, OSC1, TCAP, PD7, PD5-PD0 Input pullup current(6) PB7-PB0 (with pullup) Capacitance Ports (as input or output) RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0 Programming voltage (25C) Programming current (25C)
(4)
VOL
-- -- 0.7 x VDD
-- -- --
0.4 0.4 VDD
V
VIH
V
VIL
VSS
--
0.2 x VDD
V
IDD
-- -- -- --
3.5 1.0 1.0 7.0 -- -- --
5.25 3.25 20.0 50.0 10 1 60
mA mA A A A A A
IOZ IIn IIn COut CIn VPP IPP
-- -- 5
-- -- 15.0 --
-- -- 16.0 --
12 8 17.0 200
pF V mA
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 to +85 C, unless otherwise noted 2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, VIH = V DD-0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, V IH = VDD -0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance. 5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, VIH = V DD -0.2 V. 6. Input pullup current measured with VIL = 0.2 V.
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Advance Information 135
Freescale Semiconductor, Inc.
Electrical Specifications 12.7 3.3-Vdc Electrical Characteristics
Characteristic(1) Output voltage ILoad = 10.0 A ILoad = -10.0 A Output high voltage (ILoad = -0.2 mA) PA7-PA0, PB7-PB0, PC6-PC0, TCMP, PD7, PD0 (ILoad = -0.4 mA) PD5-PD1 (ILoad = -1.5 mA) PC7 Symbol VOL VOH Min -- VDD -0.1 Typ(2) -- -- Max 0.1 -- Unit V
VOH
VDD -0.3 VDD -0.3 VDD -0.3
-- -- --
-- -- --
V
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Output low voltage (ILoad = 0.4mA) PA7-PA0, PB7-PB0, PC6-PC0, PD7, PD5-PD0, TCMP (ILoad = 6 mA) PC7 Input high voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Input low voltage PA7-PA0, PB7-PB0, PC7-PC0, PD7, PD5-PD0, TCAP, IRQ, RESET, OSC1 Supply current (3.0-3.6 Vdc @ fOP = 1.0 MHz) Run(3) Wait Stop(5) 25C -40 to 85C I/O ports hi-Z leakage current PA7-PA0, PB7-PB0 (without pullup) PC7-PC0, PD7, PD5-PD0 Input current RESET, IRQ, OSC1, TCAP, PD7, PD5-PD0 Input pullup current(6) PB7-PB0 (with pullup) Capacitance Ports (as input or output) RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
(4)
VOL
-- -- 0.7 x VDD
-- -- --
0.3 0.3 VDD
V
VIH
V
VIL
VSS
--
0.2 x VDD
V
IDD
-- -- -- --
1.0 500 1.0 2.5 --
1.6 900 8 20 10
mA A A A A A A
IOZ IIn IIn COut CIn
--
-- 0.5
-- --
1 20
-- --
-- --
12 8
pF
1. VDD = 3.3 Vdc 0.3 Vdc, VSS = 0 Vdc, TA = -40 to +85 C, unless otherwise noted 2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD-0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, V IH = VDD -0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance. 5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V, VIH = V DD-0.2 V. 6. Input pullup current measured with VIL = 0.2 V.
Advance Information 136 Electrical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC705C9A -- Rev. 4.0 MOTOROLA
Freescale Semiconductor, Inc.
Electrical Specifications 3.3-Vdc Electrical Characteristics
5.00 mA
VDD = 5.5 V T = -40 to 85
)ID NG TI A ER OP
D
4.00 mA SUPPLY CURRENT (IDD)
N RU
(
3.00 mA
IT I D WA
D
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2.00 mA
1.00 mA
50 A
STOP IDD (MHz)
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL / 2)
Figure 12-2. Maximum Supply Current vs Internal Clock Frequency, VDD = 5.5 V
SUPPLY CURRENT (IDD)
1.00 mA
RU N
( OP ER
TID
AT ING
I WA
D
500 mA
STOP IDD 0.5 MHz 1.0 MHz
Figure 12-3. Maximum Supply Current vs Internal Clock Frequency, VDD = 3.6 V
MC68HC705C9A -- Rev. 4.0 MOTOROLA Electrical Specifications For More Information On This Product, Go to: www.freescale.com
)I
1.50 mA
VDD = 3.6 V T = -40 to 85
DD
Advance Information 137
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Electrical Specifications 12.8 5.0-Vdc Control Timing
Characteristic(1) Frequency of operation Crystal External clock Internal pperating frequency (fOSC / 2) Crystal External clock Symbol fOSC Min -- DC -- DC 480 -- -- 1.5 Max 4.2 4.2 2.1 2.1 -- 100 100 -- Unit MHz
fOP tCYC tOXOV tILCH tRL tRESL tTH, tTL tTLTL tILIH tILIL tOH,tOL
MHz ns ms ms tCYC tCYC ns tCYC ns tCYC ns
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Cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width
4.0 125
(3)
-- -- -- -- -- --
125
(4)
90
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 to +85 C, unless otherwise noted 2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution. 3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC. 4. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC.
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Electrical Specifications 3.3-Vdc Control Timing
12.9 3.3-Vdc Control Timing
Characteristic(1) Frequency of operation Crystal External clock Internal operating frequency (fOSC / 2) Crystal External clock Symbol fOSC Min -- DC -- DC 1000 -- -- 1.5 Max 2.0 2.0 1.0 1.0 -- 100 100 -- Unit MHz
fOP tCYC tOXOV tILCH tRL tRESL tTH, tTL tTLTL tILIH tILIL tOH,tOL
MHz ns ms ms tCYC tCYC ns tCYC ns tCYC ns
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Cycle time Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Timer Resolution(2) Input capture pulse width Input capture pulse period Interrupt pulse width low (edge-triggered) Interrupt pulse period OSC1 pulse width
4.0 125
(3)
-- -- -- -- -- --
250
(4)
200
1. VDD = 3.3Vdc 0.3 Vdc, VSS = 0 Vdc, TA = -40 to +85C, unless otherwise noted 2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC ), this is the limiting minimum factor
in determining the timer resolution.
3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture
interrupt service routine plus 24 tCYC.
4. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service
routine plus 19 tCYC.
tTLTL* TCAP PIN
tTH*
tTL*
* Refer to timer resolution data in 12.8 5.0-Vdc Control Timing and 12.9 3.3-Vdc Control Timing.
Figure 12-4. TCAP Timing Relationships
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Electrical Specifications
tILIL IRQ PIN tILIH
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz) or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to execute the interrupt service routine plus 19 tCYC cycles.
Freescale Semiconductor, Inc...
NORMALLY USED WITH WIRED-OR CONNECTION
IRQ1 . . . IRQN
tILIH
IRQ (INTERNAL)
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the next interrupt is recognized
Figure 12-5. External Interrupt Timing
OSC(1) tRL RESET tILIH IRQ(2) 4064 tCYC IRQ(3)
INTERNAL CLOCK
3FFE Notes: 1. Represents the internal clocking of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level- and edge-sensitive mask option 4. RESET vector address shown for timing example
3FFE
3FFE
3FFE
3FFE
3FFF4
RESET OR INTERRUPT VECTOR FETCH
Figure 12-6. STOP Recovery Timing Diagram
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Electrical Specifications 3.3-Vdc Control Timing
(NOTE 1) VDD
OSC1 PIN(2) 4064 tCYC INTERNAL CLOCK(3)
INTERNAL ADDRESS BUS(3)
3FFE
3FFE
3FFE
3FFE
3FFE
3FFE
3FFF
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INTERNAL DATA BUS(3) (NOTE 4)
NEW PCH
NEW PCL
RESET PIN
Notes: 1. Power-on reset threshold is typically between 1 V and 2 V. 2. OSC1 line is meant to represent time only, not frequency. 3. Internal clock, internal address bus, and internal data bus are not available externally. 4. RESET outputs VOL during 4064 POR cycles.
Figure 12-7. Power-On Reset Timing Diagram
INTERNAL CLOCK(1)
INTERNAL ADDRESS BUS(1)
3FFE
3FFE
3FFE
3FFE
3FFF
NEW PC
INTERNAL DATA BUS(1) RESET(2) tRL
NEW PCH
NEW PCL
OP CODE
Notes: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 12-8. External Reset Timing
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Electrical Specifications 12.10 5.0-Vdc Serial Peripheral Interface Timing
No. Characteristic(1) Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time (time to data active from high-impedance state) Slave disable time (hold time to high-impedance state) Data valid Master (before capture edge) Slave (after enable edge)(3) Data hold time (outputs) Master (after capture edge) slave (After Enable Edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Symbol fOP(M) fOP(S) tCYC(M) tCYC(S) tLEAD(M) tLEAD(S) tLAG(M) tLAG(S) tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA tDIS tV(M) tV(S) tHO(M) tHO(S) tRM tRS tFM tFS Min dc dc 2.0 480
(2)
Max 0.5 2.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 120 240 -- 240 -- -- 100 2.0 100 2.0
Unit fOP MHz tCYC ns ns
2
Freescale Semiconductor, Inc...
240
(2)
3
ns
720 340 190 340 190 100 100 100 100 0 -- 0.25 -- 0.25 0 -- -- -- --
4
ns
5
ns
6
ns
7 8 9 10
ns ns ns tCYC(M) ns tCYC(M) ns ns s ns s
11
12
13
1. VDD = 5.0 Vdc 10%; VSS = 0 Vdc, TA = -40 to +85C, unless otherwise noted. Refer to Figure 12-9 and Figure 12-10. 2. Signal production depends on software. 3. Assumes 200 pF load on all SPI pins.
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Electrical Specifications 3.3- Vdc Serial Peirpheral Interface Timing
12.11 3.3- Vdc Serial Peirpheral Interface Timing
No. Characteristic(1) Operating frequency Master Slave 1 Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time (time to data active from high-impedance state) Slave disable time (hold time to high-impedance state) Data valid Master (before capture edge) Slave (after enable edge)(3) Data hold time (outputs) Master (after capture edge) Slave (after enable edge) Rise time (20% VDD to 70% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Fall time (70% VDD to 20% VDD, CL = 200 pF) SPI outputs (SCK, MOSI, and MISO) SPI inputs (SCK, MOSI, MISO, and SS) Symbol fOP(M) fOP(S) tCYC(M) tCYC(S) tLEAD(M) tLEAD(S) tLAG(M) tLAG(S) tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA tDIS tV(M) tV(S) tHO(M) tHO(S) tRM tRS tFM tFS Min dc dc 2.0 1.0
(2)
Max 0.5 1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250 500 -- 500 -- -- 200 2.0 200 2.0
Unit fOP MHz tCYC s ns
2
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500
(2)
3
1.5 720 400 720 400 200 200 200 200 0 -- 0.25 -- 0.25 0 -- -- -- --
ns s ns
4
5
ns
6
ns
7 8 9 10
ns ns ns tCYC(M) ns tCYC(M) ns ns s ns s
11
12
13
1. VDD = 3.3 Vdc 0.3 Vdc; VSS = 0 Vdc, T A = -40 to +85 C, unless otherwise noted. Refer to Figure 12-9 and Figure 12-10. 2. Signal production depends on software. 3. Assumes 200 pF load on all SPI pins.
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Electrical Specifications
SS (INPUT)
SS pin of master held high. 1 12 5 4 12 13 13 12
SCK (CPOL = 0) (OUTPUT)
NOTE
SCK (CPOL = 1) (OUTPUT)
NOTE
5 4 6 7 LSB IN 10 BIT 6-1 11 (ref) MASTER LSB OUT 12
MISO (INPUT)
MSB IN 10 (ref) 11 MASTER MSB OUT 13
BIT 6-1
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MOSI (OUTPUT)
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS (INPUT)
SS pin of master held high. 1 13 5 4 12 13 NOTE 6 7 LSB IN 10 BIT 6-1 11 MASTER LSB OUT 12 12 NOTE
SCK (CPOL = 0) (OUTPUT)
SCK (CPOL = 1) (OUTPUT)
5 4
MISO (INPUT) 10 (ref) MOSI (OUTPUT) 13
MSB IN 11 MASTER MSB OUT
BIT 6-1
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1) Figure 12-9. SPI Master Timing Diagram
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Electrical Specifications 3.3- Vdc Serial Peirpheral Interface Timing
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) MSB IN MSB OUT 7 10 BIT 6-1 BIT 6-1 11 LSB IN 5 4 12 13 SLAVE LSB OUT 11 9 NOTE 5 4 13 12 3
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Note: Not defined but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) 5 4 10 NOTE SLAVE 6 MOSI (INPUT) MSB IN MSB OUT 7 10 BIT 6-1 12 BIT 6-1 11 LSB IN 13 9 SLAVE LSB OUT 5 4 3 13 12
Note: Not defined but normally LSB of character previously transmitted.
b) SPI Slave Timing (CPHA = 1) Figure 12-10. SPI Slave Timing Diagram
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Electrical Specifications
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Section 13. Mechanical Specifications
13.1 Contents
13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . . 150
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13.3 13.4 13.5 13.6
13.2 Introduction
This section describes the dimensions of the plastic dual in-line package (DIP), plastic shrink dual in-line package (SDIP), plastic leaded chip carrier (PLCC), and quad flat pack (QFP) MCU packages. Package dimensions available at the time of this publication are provided in this section. To make sure that you have the latest case outline specifications, contact one of the following: * * Local Motorola Sales Office World Wide Web at http://www.motorola.com/semiconductors
Follow World Wide Web on-line instructions to retrieve the current mechanical specifications.
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Mechanical Specifications 13.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03)
NOTES: 1.POSITION TOLERANCE OF LEADS (D), SHALL BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITIONS, IN RELATION TO SEATING PLANE AND EACH OTHER. 2.DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3.DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 1 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 1 0.020 0.040
40
21
B
1 20
A C
L N J
Freescale Semiconductor, Inc...
H
G
F
D
K
SEATING PLANE
M
DIM A B C D F G H J K L M N
Figure 13-1. 40-Pin Plastic DIP Package (Case 711-03)
13.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01)
-A42 22 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
-B1 21
L C H
-TSEATING PLANE
F D 42 PL 0.25 (0.010)
M
G TA
S
N K J 42 PL 0.25 (0.010)
M
M TB
S
DIM A B C D F G H J K L M N
INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.032 0.046 0.070 BSC 0.300 BSC 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 5.08 3.94 0.56 0.36 1.17 0.81 1.778 BSC 7.62 BSC 0.38 0.20 3.43 2.92 15.24 BSC 15 0 1.02 0.51
Figure 13-2. 42-Pin Plastic SDIP Package (Case 858-01)
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Mechanical Specifications 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
13.5 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
B 0.007(0.180)M T U L-M S N S L-M S N S
-N-
Y BRK
D
0.007(0.180) M T
Z -L-M-
Freescale Semiconductor, Inc...
V
44 1
W
D
X VIEW D-D
G1 0.010 (0.25) S T
L-M S N S
A R Z
0.007(0.180) M T 0.007(0.180) M T
L-M S N S L-M S N S H 0.007(0.180)M T L-M S N S
J E C G G1 0.010 (0.25) S T L-M S N S 0.004 (0.10) -TVIEW S
SEATING PLANE K
K1
F 0.007(0.180)M T VIEW S L-M S N S
NOTES: 1.DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOLDERS EXITS PLASTIC BODY AT MOLD PARTING LINE. 2.DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3.DIMENSION R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5.CONTROLLING DIMENSION: INCH. 6.THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF THE MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7.DIMINSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTUSION(S) SHALL NOT CAUSE THE H DIMINSION TO BE GREATER THAN 0.037 (0.940150). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMINISION TO SMALLER THAN 0.025 (0.635).
INCHES DIM A B C E F G H J K R U V W X Y Z G1 K1 MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.610 0.630 0.040
MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 0.50 2 10 15.50 16.00 1.02
Figure 13-3. 44-Lead PLCC (Case 777-02)
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Mechanical Specifications 13.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01)
L
33 34
23 22 S S
D
D
B -A,B,DB
S
0.20 (0.008) M C A-B 0.05 (0.002) A-B
-A-
-BB
Freescale Semiconductor, Inc...
L
V
DETAIL A
44 1 11 12
0.20 (0.008)
M
H A-B
S
DETAIL A
F -DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B S 0.20 (0.008) M H A-B
BASE METAL S
D
S
J
S
N D
D
S
M
DETAIL C
DATUM PLANE
0.20 (0.008)
M
C A-B
S
D
S
SECTION B-B CE -CSEATING PLANE
-HH
0.01 (0.004) G M M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A , B AND D TO BE DETERMINED AT DATUM PLANE H . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE C . 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.45 2.10 0.45 0.30 2.10 2.00 0.40 0.30 0.80 BSC 0.25 0.23 0.13 0.95 0.65 8.00 REF 10 5 0.17 0.13 7 0 0.30 0.13 12.95 13.45 0.13 0 12.95 13.45 0.40 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC 0.010 0.005 0.009 0.026 0.037 0.315 REF 10 5 0.005 0.007 7 0 0.005 0.012 0.510 0.530 0.005 0 0.510 0.530 0.016 0.063 REF
T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
Figure 13-4. 44-Lead QFP (Case 824A-01)
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Section 14. Ordering Information
14.1 Contents
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
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14.3
14.2 Introduction
This section contains ordering information for the available package types.
14.3 MC Order Numbers
Table 14-1 shows the MC order numbers for the available package types. Table 14-1. MC Order Numbers
Package Type 40-pin plastic dual in-line package (DIP) 42-pin shrink dual in-line package (SDIP) 44-lead plastic leaded chip carrier (PLCC) 44-pin quad flat pack (QFP)
P = Plastic dual in-line package (PDIP) B = Shrink dual in-line package (SDIP) FN = Plastic-leaded chip carrier (PLCC) FB = Quad flat pack (QFP)
Temperature Range -40C to 85C -40C to 85C
Order Number MC68HC705C9ACP MC68HC705C9ACB
-40C to 85C MC68HC705C9ACFN -40C to 85C MC68HC705C9ACFB
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Ordering Information
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Appendix A. EPROM Programming
A.1 Contents
A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Programming Register (PROG) . . . . . . . . . . . . . . . . . . . . . . .154
Freescale Semiconductor, Inc...
A.3 A.4 A.5
A.2 Introduction
This section describes programming of the EPROM.
A.3 Bootloader Mode
Table A-1. Operating Modes
RESET IRQ VSS to VDD VTST TCAP VSS to VDD VDD Mode User Bootloader
Bootloader mode is entered upon the rising edge of RESET if the IRQ is at VTST and the TCAP pin is at logic one. The bootloader code resides in the ROM from $3F00 to $3FEF. This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootload function does not have to be done from an external EPROM, but it may be done from a host. The user code must be a one-to-one correspondence with the internal EPROM addresses.
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EPROM Programming A.4 Bootloader Functions
Three pins are used to select various bootloader functions: PD5, PD4, and PD3. Two other pins, PC6 and PC7, are used to drive the PROG LED and the VERF LED, respectively. The programming modes are shown in Table A-2. Table A-2. Bootloader Functions
PD5 PD4 0 0 1 X PD3 0 1 0 X Mode Program/verify Verify only Load RAM and execute Secure
Freescale Semiconductor, Inc...
0 0 0 1
A.5 Programming Register (PROG)
This register is used to program the EPROM array. To program a byte of EPROM, set LATCH, write data to the desired address, and set EPGM for tEPGM.
$001X Read: LATCH Write: Reset: 0 0 0 0 0 0 0 0 EPGM Bit 7 6 5 4 3 2 1 Bit 0
Figure A-1. EPROM Programming Register LATCH -- EPROM Latch Control Bit This read/write bit controls the latching of the address and data buses when programming the EPROM. 1 = Address and data buses latched when the following instruction is a write to 1 of the EPROM locations. Normal reading is disabled if LATCH = 1. 0 = EPROM address and data bus configured for normal reading
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EPROM Programming Programming Register (PROG)
EPGM -- EPROM Program Control Bit This read/write bit controls whether the programming voltage is applied to the EPROM array. For programming, this bit can be set only if the LATCH bit has been set previously. Both EPGM and LATCH cannot be set in the single write. 1 = Programming voltage applied to EPROM array 0 = Programming voltage not applied to EPROM array
NOTE:
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Bits 7-3 and bit 1 MUST be set to 0 when writing to the EPROM programming register.
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EPROM Programming
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Appendix B. M68HC05Cx Family Feature Comparisons
Refer to Table B-1 for a comparison of the features for all the M68HC05C Family members.
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Table B-1. M68HC05Cx Feature Comparison
705C4A -- 4160 YES 176 176 176 176-304 176-304 176 176 176-352 176-352 176-352 NO YES YES YES NO YES NO YES NO -- -- 7596-7740 7596-7740 -- -- -- -- 15,760-15,936 7744 7744 -- -- 12,096 12,096 15,760-15,936 15,760-15,936 -- -- 12,096-15,936 YES 176-352 C8 C8A 705C8 705C8A C12 C12A C9 C9A/C9E 705C9 705C9A
C4
C4A
MC68HC705C9A -- Rev. 4.0
-- $1FDF (IRQ/SEC) NO NO NO NO $1FDF (IRQ/RAM/SEC) $3FDF (IRQ/RAM) $3FDF (IRQ/RAM) $1FDF (IRQ/RAM/ SEC) NO $1FF0-$1FF1 NO NO NO NO $3FDF (IRQ/RAM) $3FDF (IRQ/RAM) $1FF0-$1FF1 NO NO NO $3FF0-$3FF1 YES MOR SELECTABLE NO YES MASK OPTION NO NO HIGH CURRENT STANDARD HIGH CURRENT PD7, 5-0 INPUT ONLY TWO TYPES SOFTWARE+ MOR SOFTWARE+ MOR SELECTABLE MASK OPTION 64 ms (@4 MHz OSC) YES PD7, 5-0 INPUT ONLY PD7, 5-0 INPUT ONLY YES MASK OPTION HIGH CURRENT HIGH CURRENT PD7, 5-0 INPUT ONLY YES MASK OPTION SOFTWARE 64 ms SOFTWARE (@4 MHz OSC) SELECTABLE YES PD7, 5-0 INPUT ONLY STANDARD YES MOR SELECTABLE YES MASK OPTION YES MASK OPTION HIGH CURRENT STANDARD PD7, 5-0 INPUT ONLY NO -- YES MASK OPTION HIGH CURRENT PD7, 5-0 BIDIRECTIONAL YES SOFTWARE PD7, 5-0 BIDIRECTIONAL YES SOFTWARE NO YES MOR SELECTABLE STANDARD HIGH CURRENT PD7, 5-0 BIDIRECTIONAL YES SOFTWARE PD7, 5-0 BIDIRECTIONAL TWO TYPES SOFTWARE+ MOR 64 ms SOFTWARE (@4MHz OSC) SELECTABLE SOFTWARE SELECTABLE SOFTWARE SELECTABLE SOFTWARE+ MOR SELECTABLE YES MOR 64 ms (@4 MHz OSC) -- CLR $1FF0 -- CLR $1FF0 WRITE $55/$AA TO $001D WRITE $55/$AA TO $001D OR CLR $1FF0 YES CLR $3FF0 CLR $3FF0 WRITE $55/$AA WRITE $55/$AA WRITE $55/$AA TO $001D TO $001D TO $001D WRITE $55/$AA TO $001D OR CLR $3FF0 NO NO YES YES YES YES (C9A MODE) YES NO NO NO NO NO NO COP/CLOCK MONITOR PROGRAMMABLE COP/CLOCK MONITOR NO NO NO NO POR/COP/ CLOCK MONITOR POR/COP/ CLOCK MONITOR POR/COP/ CLOCK MONITOR POR/C9A COP/ CLOCK MONITOR NO NO MASK OPTION MASK OPTION MASK OPTION NO NO NO MOR SELECTABLE (C12A MODE)
MOTOROLA
USER ROM
4160
4160
USER EPROM
--
CODE SECURITY
NO
YES
RAM
176
176
OPTION REGISTER (IRQ/RAM/ SEC)
NO
NO
MASK OPTION REGISTER(S)
NO
NO
PORTB KEYSCAN (PULLUP/ INTERRUPT)
NO
YES MASK OPTION
PC7 DRIVE
STANDARD
HIGH CURRENT
PORT D
PD7, 5-0 PD7, 5-0 PD7, 5-0 INPUT ONLY INPUT ONLY INPUT ONLY
COP
NO
YES
COP ENABLE
--
MASK OPTION
COP TIMEOUT
--
64 ms (@4 MHz OSC)
Freescale Semiconductor, Inc.
M68HC05Cx Family Feature Comparisons For More Information On This Product, Go to: www.freescale.com
COP CLEAR
--
CLR $1FF0
CLOCK MONITOR
NO
NO
ACTIVE RESET
NO
NO
STOP DISABLE
NO
MASK OPTION
M68HC05Cx Family Feature Comparisons
Advance Information
Notes: 1. The expanded RAM map (from $30-$4F and $100-$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and MC68HC05C8A. 2. The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP.
158
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC:
Freescale Semiconductor, Inc...
Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
(c) Motorola, Inc. 2002
MC68HC705C9A/D
For More Information On This Product, Go to: www.freescale.com

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